Xilinx 7 Series User Manual page 37

Table 2-8: PLL Ports (Cont'd)
Port
PLL0REFCLKSEL[2:0]
PLL1REFCLKSEL[2:0]
PLL0RESET
PLL1RESET
PLL0FBCLKLOST
PLL1FBCLKLOST
PLL0LOCK
PLL1LOCK
PLL0REFCLKLOST
PLL1REFCLKLOST
Table 2-9: PLL Attributes
PLL0_CFG
PLL1_CFG
PLL0_FBDIV
PLL1_FBDIV
PLL0_FBDIV_45
PLL1_FBDIV_45
PLL0_LOCK_CFG
PLL1_LOCK_CFG
PLL0_REFCLK_DIV
PLL1_REFCLK_DIV
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Direction Clock Domain
In Async
In Async
Out PLL0LOCKDETCLK
PLL1LOCKDETCLK
Out Async
Out PLL0LOCKDETCLK
PLL1LOCKDETCLK
Attribute
27-bit Hex
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Input to dynamically select the input reference clock to the
PLL. This input should be set to 3'b001 when only one
clock source is connected to the PLL reference clock
selection multiplexer.
Reset must be applied to the PLL after changing the
reference clock input.
000: Reserved
001: GTREFCLK0 selected
010: GTREFCLK1 selected
011: GTEASTREFCLK0 selected
100: GTEASTREFCLK1 selected
101: GTWESTREFCLK0 selected
110: GTWESTREFCLK1 selected
111: GTGREFCLK0 (PLL0) or GTGREFCLK1
(PLL1) selected
This active-High port resets the dividers inside the PLL as
well as the PLL lock indicator and status block.
A High on this signal indicates the feedback clock from the
PLL feedback divider to the phase frequency detector of the
PLL is lost.
This active-High PLL frequency lock signal indicates that
the PLL frequency is within predetermined tolerance. The
transceiver and its clock outputs are not reliable until this
condition is met.
A High on this signal indicates the reference clock to the
phase frequency detector of the PLL is lost.
Type
Reserved. Configuration setting for the PLL. The
recommended value from the 7 Series FPGAs
Transceivers Wizard should be used.
Integer
PLL feedback divider setting as shown in
page 35. Valid settings are 1, 2, 3, 4, and 5.
Integer PLL feedback divider settings as shown in
Figure 2-10, page
9-bit Hex
Reserved. The recommended value from the 7 Series
FPGAs Transceivers Wizard should be used.
Integer
PLL reference clock divider M settings as shown in
Figure 2-10, page
Description
Description
Figure 2-10,
35. Valid settings are 4 and 5.
35. Valid settings are 1 and 2.
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PLL
37