Xilinx 7 Series User Manual page 194

Chapter 4: Receiver
Table 4-37: RX Clock Correction Attributes (Cont'd)
Attribute
CLK_COR_SEQ_1_ENABLE
CLK_COR_SEQ_1_1
CLK_COR_SEQ_1_2
CLK_COR_SEQ_1_3
CLK_COR_SEQ_1_4
CLK_COR_SEQ_2_USE
CLK_COR_SEQ_2_ENABLE
CLK_COR_SEQ_2_1
CLK_COR_SEQ_2_2
CLK_COR_SEQ_2_3
CLK_COR_SEQ_2_4
RX_DATA_WIDTH
194
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Type
4-bit Binary Mask enable bit for the first clock correction sequence.
CLK_FOR_SEQ_1_ENABLE[0] is the mask bit for CLK_COR_SEQ_1_1.
CLK_FOR_SEQ_1_ENABLE[1] is the mask bit for CLK_COR_SEQ_1_2.
CLK_FOR_SEQ_1_ENABLE[2] is the mask bit for CLK_COR_SEQ_1_3.
CLK_FOR_SEQ_1_ENABLE[3] is the mask bit for CLK_COR_SEQ_1_4.
When CLK_FOR_SEQ_1_ENABLE[*] is 0, the corresponding
CLK_COR_SEQ_1_* is either considered as a don't care or is matched
automatically without a comparison.
When CLK_FOR_SEQ_1_ENABLE[*] is 1, the corresponding
CLK_COR_SEQ_1_* is compared for a match.
10-bit Binary First clock correction sequence 1 to be compared when
CLK_FOR_SEQ_1_ENABLE[0] = 1.
10-bit Binary First clock correction sequence 2 to be compared when
CLK_FOR_SEQ_1_ENABLE[1] = 1.
10-bit Binary First clock correction sequence 3 to be compared when
CLK_FOR_SEQ_1_ENABLE[2] = 1.
10-bit Binary First clock correction sequence 4 to be compared when
CLK_FOR_SEQ_1_ENABLE[3] = 1.
String Set to TRUE if the second clock correction sequence (CLK_COR_SEQ_2_*) is
used in addition to the CLK_COR_SEQ_1_* that is always used.
4-bit Binary Mask enable bit for the second clock correction sequence.
CLK_FOR_SEQ_2_ENABLE[0] is the mask bit for CLK_COR_SEQ_2_1.
CLK_FOR_SEQ_2_ENABLE[1] is the mask bit for CLK_COR_SEQ_2_2.
CLK_FOR_SEQ_2_ENABLE[2] is the mask bit for CLK_COR_SEQ_2_3.
CLK_FOR_SEQ_2_ENABLE[3] is the mask bit for CLK_COR_SEQ_2_4.
When CLK_FOR_SEQ_2_ENABLE[*] is 0, the corresponding
CLK_COR_SEQ_2_* is either considered as a don't care or is matched
automatically without a comparison.
When CLK_FOR_SEQ_2_ENABLE[*] is 1, the corresponding
CLK_COR_SEQ_2_* is compared for a match.
10-bit Binary Second clock correction sequence 1 to be compared when
CLK_FOR_SEQ_2_ENABLE[0] = 1
10-bit Binary Second clock correction sequence 2 to be compared when
CLK_FOR_SEQ_2_ENABLE[1] = 1
10-bit Binary Second clock correction sequence 3 to be compared when
CLK_FOR_SEQ_2_ENABLE[2] = 1
10-bit Binary Second clock correction sequence 4 to be compared when
CLK_FOR_SEQ_2_ENABLE[3] = 1
Integer Sets the bit width of the RXDATA port. When 8B/10B encoding is enabled,
RX_DATA_WIDTH must be set to 20 or 40. Valid settings are 16, 20, 32, and
40.
See Interface Width Configuration, page 214
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for more details.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016