Xilinx 7 Series User Manual page 177

Table 4-30: RX Buffer Bypass Attributes (Cont'd)
RX_XCLK_SEL
RXPH_CFG
RXPH_MONITOR_SEL
RXPHDLY_CFG
RXDLY_CFG
RXDLY_LCFG
RXDLY_TAP_CFG
RX_DDI_SEL
RXSYNC_MULTILANE
RXSYNC_SKIP_DA
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Attribute Type
String
24-bit Binary
5-bit Binary
24-bit Binary
16-bit Binary
9-bit Binary
16-bit Binary
6-bit Binary
1-bit Binary
1-bit Binary
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RX Buffer Bypass
Description
Selects the clock source used to drive the RX
parallel clock domain (XCLK).
RXREC: Selects the RX recovered clock as
source of XCLK. Used when using the RX
elastic buffer.
RXUSR: Selects RXUSRCLK as the source of
XCLK. Used when bypassing the RX elastic
buffer.
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
RX phase and delay alignment configuration.
RXPHDLY_CFG[19] = 1 is used to set the RX
delay alignment tap to the full range of ±4 ns.
RXPHDLY_CFG[19] = 0 is used to set the RX
delay alignment tap to the half range of ±2 ns.
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
RX data delay insertion select.
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
Indicates whether the lane is used as part of a
multi-lane interface. Only valid on RX buffer
bypass master lane in auto mode.
0: This lane is used in single-lane mode.
1: This lane is used in multi-lane mode.
Control to skip delay alignment procedure. Only
valid on buffer bypass master lane in auto mode.
0: RX delay alignment procedure occurs.
1: RX delay alignment procedure is skipped.
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