Xilinx 7 Series User Manual page 176

Chapter 4: Receiver
Table 4-29: RX Buffer Bypass Ports (Cont'd)
RXPHALIGNDONE
RXPHMONITOR
RXPHSLIPMONITOR
RXDLYSRESETDONE
RXSYNCMODE
RXSYNCALLIN
RXSYNCIN
RXSYNCOUT
RXSYNCDONE
Table 4-30
Table 4-30: RX Buffer Bypass Attributes
RXBUF_EN
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Port Dir
Out
Out
Out
Out
In
In
In
Out
Out
defines the RX buffer attributes.
Attribute Type
String
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Clock Domain
Async RX phase alignment done. When the auto
RX phase and delay alignment are used,
the second rising edge of
RXPHALIGNDONE detected after
RXDLYSRESETDONE assertion
indicates RX phase and delay alignment
are done.
Async RX phase alignment monitor.
Async RX phase alignment slip monitor.
Async RX delay alignment soft reset done.
Async 0: RX Buffer Bypass Slave lane
1: RX Buffer Bypass Master lane
This input is not used in multi-lane
manual mode.
Async Single-lane auto mode: Connect this
input to its own RXPHALIGNDONE.
Multi-lane auto mode: Connect this input
to the ANDed signal of
RXPHALIGNDONE of the master and
all slave lanes.
Multi-lane manual mode: This input is
not used in multi-lane manual mode.
Async Only valid in multi-lane auto mode
applications. Connect this input to
RXSYNCOUT from RX buffer bypass
master lane.
Async Only valid for RX buffer bypass master
lane in multi-lane auto mode
applications. Connect this signal to the
RXSYNCIN of each lane within the
multi-lane application.
Async Indicates RX Buffer Bypass alignment
procedure completion. Only valid for RX
buffer bypass master lane in auto mode
operation.
Description
Use or bypass the RX elastic buffer.
TRUE: Uses the RX elastic buffer (default).
FALSE: Bypasses the RX elastic buffer
(advanced feature).
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Description