Xilinx 7 Series User Manual page 266

Appendix D: DRP Address Map of the GTP Transceiver
Table D-1: DRP Map of GTPE2_COMMON Primitive (Cont'd)
DRP Address
DRP Bits
(Hex)
15:0
001A
15:0
001B
15:0
001C
15:0
0024
15:0
0028
7:0
0029
8:0
002A
13:9
002B
7
002B
5:0
002B
15:0
002C
10:0
002D
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R/W Attribute Name
R/W BIAS_CFG
R/W BIAS_CFG
R/W BIAS_CFG
R/W RSVD_ATTR1
R/W PLL1_INIT_CFG
R/W PLL1_INIT_CFG
R/W PLL1_LOCK_CFG
R/W PLL1_REFCLK_DIV
R/W PLL1_FBDIV_45
R/W PLL1_FBDIV
R/W PLL1_CFG
R/W PLL1_CFG
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Attribute Attribute
Bits Encoding
31:16 0-65535
47:32 0-65535
63:48 0-65535
15:0 0-65535
15:0 0-65535
23:16 0-255
8:0 0-511
1
4:0
2
4
0
5
1
2
5:0 3
4
5
15:0 0-65535
26:16 0-2047
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP Binary
Encoding
0-65535
0-65535
0-65535
0-65535
0-65535
0-255
0-511
16
0
0
1
16
0
1
2
3
0-65535
0-2047