Xilinx Virtex-5 FPGA ML561 Manuals

Manuals and User Guides for Xilinx Virtex-5 FPGA ML561. We have 6 Xilinx Virtex-5 FPGA ML561 manuals available for free PDF download: User Manual

Xilinx Virtex-5 FPGA ML561 User Manual (385 pages)

Brand: Xilinx | Category: Computer Hardware | Size: 13.35 MB

Revision History

3
- Table of Contents
  9
Preface: about this Guide

21
- Additional Documentation
  
  21
- Additional Support Resources
  
  22
- Typographical Conventions
  
  22
  - Online Document
    23
Chapter 1: Clock Resources

25
- Global and Regional Clocks
  
  25
  - Global Clocks
    25
  - Regional Clocks and I/O Clocks
    25
- Global Clocking Resources
  
  26
  - Global Clock Inputs
    26
    
    Global Clock Input Buffer Primitives
    26
  - Clock Gating for Power Savings
    26
  - Global Clock Buffers
    27
    
    Global Clock Buffer Primitives
    28
    
    Additional Use Models
    36
  - Clock Tree and Nets - GCLK
    38
  - Clock Regions
    38
- Regional Clocking Resources
  
  40
  - Clock Capable I/O
    40
  - I/O Clock Buffer - BUFIO
    41
    
    BUFIO Primitive
    41
    
    BUFIO Use Models
    41
  - Regional Clock Buffer - BUFR
    42
    
    BUFR Primitive
    43
    
    BUFR Attributes and Modes
    44
    
    BUFR Use Models
    45
  - Regional Clock Nets
    46
- VHDL and Verilog Templates
  
  46
Chapter 2: Clock Management Technology

47
- Clock Management Summary
  
  47
- DCM Summary
  
  48
- DCM Primitives
  
  50
  - DCM_BASE Primitive
    50
  - DCM_ADV Primitive
    51
- DCM Ports
  
  51
- DCM Attributes
  
  58
  - CLKDV_DIVIDE Attribute
    58
  - CLKFX_MULTIPLY and CLKFX_DIVIDE Attribute
    58
  - CLKIN_PERIOD Attribute
    58
  - CLKIN_DIVIDE_BY_2 Attribute
    59
  - CLKOUT_PHASE_SHIFT Attribute
    59
  - CLK_FEEDBACK Attribute
    59
  - DESKEW_ADJUST Attribute
    60
  - DFS_FREQUENCY_MODE Attribute
    60
  - DLL_FREQUENCY_MODE Attribute
    60
  - DUTY_CYCLE_CORRECTION Attribute
    60
  - DCM_PERFORMANCE_MODE Attribute
    60
  - FACTORY_JF Attribute
    61
  - PHASE_SHIFT Attribute
    61
  - STARTUP_WAIT Attribute
    61
- DCM Design Guidelines
  
  63
  - Clock Deskew
    63
    
    Clock Deskew Operation
    63
    
    Input Clock Requirements
    64
    
    Input Clock Changes
    64
    
    Output Clocks
    65
    
    DCM During Configuration and Startup
    65
    
    Deskew Adjust
    65
    
    Characteristics of the Deskew Circuit
    67
  - Frequency Synthesis
    67
    
    Frequency Synthesis Operation
    67
    
    Frequency Synthesizer Characteristics
    68
  - Phase Shifting
    68
    
    Phase-Shifting Operation
    68
    
    Interaction of PSEN, PSINCDEC, PSCLK, and PSDONE
    71
    
    Phase-Shift Overflow
    72
    
    Phase-Shift Characteristics
    72
  - Dynamic Reconfiguration
    73
- Connecting Dcms to Other Clock Resources in Virtex-5 Devices
  
  73
  - IBUFG to DCM
    73
  - DCM to BUFGCTRL
    73
  - BUFGCTRL to DCM
    73
  - PLL to and from DCM
    74
  - DCM to and from PMCD
    74
- Application Examples
  
  75
  - Standard Usage
    75
  - Board-Level Clock Generation
    75
  - Board Deskew with Internal Deskew
    77
  - Clock Switching between Two Dcms
    80
  - DCM with PLL
    81
- VHDL and Verilog Templates, and the Clocking Wizard
  
  83
- DCM Timing Models
  
  84
  - Reset/Lock
    84
  - Fixed-Phase Shifting
    85
  - Variable-Phase Shifting
    86
  - Status Flags
    87
- Legacy Support
  
  88
Chapter 3: Phase-Locked Loops (Plls)

89
- Introduction
  
  89
  - Phase Locked Loop (PLL)
    90
- General Usage Description
  
  92
  - PLL Primitives
    92
    
    PLL_BASE Primitive
    92
    
    PLL_ADV Primitive
    93
  - Clock Network Deskew
    93
  - Frequency Synthesis Only
    93
  - Jitter Filter
    94
  - Limitations
    94
    
    VCO Operating Range
    94
    
    Minimum and Maximum Input Frequency
    94
    
    Duty Cycle Programmability
    94
    
    Phase Shift
    95
  - PLL Programming
    95
    
    Determine the Input Frequency
    95
    
    Determine the M and D Values
    96
  - PLL Ports
    96
  - PLL Attributes
    98
  - PLL CLKIN1 and CLKIN2 Usage
    100
  - PLL Clock Input Signals
    101
  - Counter Control
    102
  - Clock Shifting
    103
- Detailed VCO and Output Counter Waveforms
  
  103
- Reference Clock Switching
  
  104
  - Missing Input Clock or Feedback Clock
    105
- PLL Use Models
  
  105
  - Clock Network Deskew
    105
    
    PLL with Internal Feedback
    106
  - Zero Delay Buffer
    106
  - DCM Driving PLL
    107
  - PLL Driving DCM
    108
  - PLL to PLL Connection
    109
- Application Guidelines
  
  109
  - PLL Application Example
    110
- PLL in Virtex-4 FPGA PMCD Legacy Mode
  
  111
Chapter 4: Block RAM

113
- Block RAM Summary
  
  113
- Block RAM Introduction
  
  115
- Synchronous Dual-Port and Single-Port Rams
  
  115
  - Data Flow
    115
  - Read Operation
    117
  - Write Operation
    117
  - Write Modes
    117
    
    WRITE_FIRST or Transparent Mode (Default)
    118
    
    READ_FIRST or Read-Before-Write Mode
    118
    
    NO_CHANGE Mode
    118
  - Conflict Avoidance
    119
    
    Asynchronous Clocking
    119
    
    Synchronous Clocking
    119
- Additional Block RAM Features in Virtex-5 Devices
  
  120
  - Optional Output Registers
    120
  - Independent Read and Write Port Width Selection
    120
  - Simple Dual-Port Block RAM
    121
  - Cascadable Block RAM
    122
  - Byte-Wide Write Enable
    122
  - Block RAM Error Correction Code
    123
- Block RAM Library Primitives
  
  123
- Block RAM Port Signals
  
  125
  - Clock - CLK[A|B]
    125
  - Enable - EN[A|B]
    125
  - Byte-Wide Write Enable - WE[A|B]
    125
  - Register Enable - REGCE[A|B]
    125
  - Set/Reset - SSR[A|B]
    125
  - Address Bus - ADDR[A|B]<13:#><14:#><15
    125
  - Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0
    126
  - Data-Out Buses - DO[A|B]<#:0> and DOP[A|B]<#:0
    126
  - Cascade in - CASCADEINLAT[A|B] and CASCADEINREG[A|B]
    127
  - Cascade out - CASCADEOUTLAT[A|B] and CASCADEOUTREG[A|B]
    127
  - Inverting Control Pins
    127
  - Gsr
    127
  - Unused Inputs
    127
- Block RAM Address Mapping
  
  128
- Block RAM Attributes
  
  128
- Block RAM Initialization in VHDL or Verilog Code
  
  131
- Additional RAMB18 and RAMB36 Primitive Design Considerations
  
  131
  - Optional Output Registers
    131
  - Independent Read and Write Port Width
    131
  - RAMB18 and RAMB36 Port Mapping Design Rules
    132
  - Cascadable Block RAM
    132
  - Byte-Wide Write Enable
    132
- Additional Block RAM Primitives
  
  133
- Block RAM Applications
  
  133
  - Creating Larger RAM Structures
    133
  - Block RAM SSR in Register Mode
    133
- Block RAM Timing Model
  
  134
  - Block RAM Timing Parameters
    135
  - Block RAM Timing Characteristics
    136
    
    Clock Event 1
    136
    
    Clock Event 2
    137
    
    Clock Event 4
    137
    
    Clock Event 5
    137
  - Block RAM Timing Model
    138
- Block RAM Retargeting
  
  139
- Built-In FIFO Support
  
  139
  - Multirate FIFO
    139
  - Synchronous FIFO
    140
    
    Synchronous FIFO Implementations
    141
- FIFO Architecture: a Top-Level View
  
  142
- FIFO Primitives
  
  142
- FIFO Port Descriptions
  
  143
- FIFO Operations
  
  144
  - Reset
    144
  - Operating Mode
    144
    
    Standard Mode
    144
    
    First Word Fall through (FWFT) Mode
    144
  - Status Flags
    145
    
    Empty Flag
    145
    
    Almost Empty Flag
    146
    
    Read Error Flag
    146
    
    Full Flag
    146
    
    Write Error Flag
    146
    
    Almost Full Flag
    146
- FIFO Attributes
  
  147
  - FIFO Almost Full/Empty Flag Offset Range
    148
- FIFO Timing Models and Parameters
  
  149
  - FIFO Timing Characteristics
    150
    
    Case 1: Writing to an Empty FIFO
    151
    
    Case 2: Writing to a Full or Almost Full FIFO
    152
    
    Case 3: Reading from a Full FIFO
    154
    
    Case 4: Reading from an Empty or Almost Empty FIFO
    155
    
    Case 5: Resetting All Flags
    156
    
    Case 6: Simultaneous Read and Write for Multirate FIFO
    157
- FIFO VHDL and Verilog Templates
  
  149
- FIFO Applications
  
  157
  - Cascading Fifos to Increase Depth
    157
  - Connecting Fifos in Parallel to Increase Width
    158
- Built-In Error Correction
  
  158
  - ECC Modes Overview
    159
  - Top-Level View of the Block RAM ECC Architecture
    160
  - Block RAM and FIFO ECC Primitive
    161
  - Block RAM and FIFO ECC Port Descriptions
    162
  - Block RAM and FIFO ECC Attributes
    164
  - ECC Modes of Operation
    165
    
    Standard ECC
    166
    
    ECC Encode-Only
    166
    
    ECC Decode-Only
    167
  - ECC Timing Characteristics
    168
    
    Standard ECC Read Timing (Figure 4-32)
    168
    
    Standard ECC Write Timing (Figure 4-31)
    168
    
    Decode-Only ECC Read Timing
    169
    
    Decode-Only ECC Write Timing
    169
    
    Encode-Only ECC Read Timing
    169
    
    Encode-Only ECC Write Timing
    169
  - Block RAM ECC Mode Timing Parameters
    169
  - Creating a Deliberate Error in a 72-Bit Word
    170
  - Creating Eight Parity Bits for a 64-Bit Word
    170
  - Inserting a Single or Double Bit Error into a 72-Bit Word
    170
  - Block RAM ECC VHDL and Verilog Templates
    171
- Legal Block RAM and FIFO Combinations
  
  171
Chapter 5: Configurable Logic Blocks (Clbs)

173
- CLB Overview
  
  173
  - Slice Description
    174
    
    Clb/Slice Configurations
    177
    
    Look-Up Table (LUT)
    178
    
    Storage Elements
    178
    
    Distributed RAM and Memory (Available in SLICEM Only)
    180
    
    Read Only Memory (ROM)
    190
    
    Shift Registers (Available in SLICEM Only)
    190
    
    Multiplexers
    195
    
    Designing Large Multiplexers
    196
    
    Fast Lookahead Carry Logic
    198
- CLB / Slice Timing Models
  
  200
- CLB Primitives
  
  211
  - Distributed RAM Primitives
    211
    
    Port Signals
    212
  - Shift Registers (Srls) Primitive
    213
    
    Port Signals
    213
  - Other Shift Register Applications
    214
    
    Synchronous Shift Registers
    214
    
    Static-Length Shift Registers
    214
  - Multiplexer Primitives
    215
    
    Port Signals
    215
  - Carry Chain Primitive
    215
    
    Port Signals
    216
Chapter 6: Selectio Resources

217
- I/O Tile Overview
  
  217
- Selectio Resources Introduction
  
  218
- Selectio Resources General Guidelines
  
  218
  - Virtex-5 FPGA I/O Bank Rules
    218
    
    Reference Voltage
    219
    
    REF ) Pins
    219
    
    Output Drive Source Voltage
    219
    
    CCO ) Pins
    219
  - Virtex-5 FPGA Digitally Controlled Impedance (DCI)
    220
    
    Introduction
    220
    
    DCI Cascading
    220
    
    Xilinx DCI
    223
    
    Controlled Impedance Driver (Source Termination)
    224
    
    Controlled Impedance Driver with Half Impedance (Source Termination)
    225
    
    Input Termination to VCCO (Single Termination)
    225
    
    Input Termination to VCCO/2 (Split Termination)
    226
    
    Driver with Termination to VCCO (Single Termination)
    227
    
    Driver with Termination to V CCO /2 (Split Termination)
    227
  - DCI in Virtex-5 Device I/O Standards
    229
    
    DCI Usage Examples
    230
- Virtex-5 FPGA Selectio Primitives
  
  233
  - IBUF and IBUFG
    233
  - Obuf
    233
  - Obuft
    234
  - Iobuf
    234
  - IBUFDS and IBUFGDS
    234
  - Ibufds_Diff_Out
    235
  - Obufds
    235
  - Obuftds
    235
  - Iobufds
    236
  - Virtex-5 FPGA Selectio Attributes/Constraints
    236
    
    Location Constraints
    236
    
    IOSTANDARD Attribute
    236
    
    Output Slew Rate Attributes
    237
    
    Output Drive Strength Attributes
    237
    
    PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF
    237
    
    Differential Termination Attribute
    237
  - Virtex-5 FPGA I/O Resource Vhdl/Verilog Examples
    238
- Specific Guidelines for I/O Supported Standards
  
  239
  - LVTTL (Low Voltage Transistor-Transistor Logic)
    239
  - LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor)
    241
    
    LVDCI (Low Voltage Digitally Controlled Impedance)
    243
    
    Lvdci_Dv2
    244
    
    HSLVDCI (High-Speed Low Voltage Digitally Controlled Impedance)
    246
  - PCI-X, PCI-33, PCI-66 (Peripheral Component Interconnect)
    247
  - GTL (Gunning Transceiver Logic)
    248
    
    GTL_DCI Usage
    248
  - GTLP (Gunning Transceiver Logic Plus)
    249
    
    GTLP_DCI Usage
    249
  - HSTL (High-Speed Transceiver Logic)
    250
    
    Hstl_ I_Dci, Hstl_ Iii_Dci, Hstl_ I_Dci_18, Hstl_ Iii_Dci_18
    250
    
    Hstl_ Ii_Dci, Hstl_ Iv_Dci, Hstl_ Ii_Dci_18, Hstl_ Iv_Dci_18
    251
    
    Hstl_ Ii_T_Dci, Hstl_ Ii_T_Dci_18
    251
    
    Diff_Hstl_ II, Diff_Hstl_Ii_18
    251
    
    Diff_Hstl_Ii_Dci, Diff_Hstl_Ii_Dci_18
    251
    
    Diff_Hstl_I, Diff_Hstl_I_18
    251
    
    Diff_Hstl_I_Dci, Diff_Hstl_I_Dci_18
    251
  - HSTL Class I
    252
  - Differential HSTL Class I
    253
  - HSTL Class II
    254
  - Differential HSTL Class II
    256
  - HSTL Class III
    259
  - HSTL Class IV
    260
  - HSTL_II_T_DCI (1.5V) Split-Thevenin Termination
    262
  - HSTL Class I (1.8V)
    263
  - Differential HSTL Class I (1.8V)
    264
  - HSTL Class II (1.8V)
    265
  - Differential HSTL Class II (1.8V)
    267
  - HSTL Class III (1.8V)
    270
  - HSTL Class IV (1.8V)
    271
  - HSTL_II_T_DCI_18 (1.8V) Split-Thevenin Termination
    273
  - HSTL Class I (1.2V)
    274
  - SSTL (Stub-Series Terminated Logic)
    274
    
    Sstl2_I, Sstl18_I
    275
    
    Sstl2_I_Dci, Sstl18_I_Dci
    275
    
    Sstl2_Ii, Sstl18_Ii
    275
    
    Diff_Sstl2_I, Diff_Sstl18_I
    275
    
    Diff_Sstl2_I_Dci, Diff_Sstl18_I_Dci
    275
    
    Diff_Sstl2_Ii, Diff_Sstl18_Ii
    275
  - SSTL2 Class I (2.5V)
    276
  - Differential SSTL2 Class I (2.5V)
    277
  - SSTL2 Class II (2.5V)
    279
  - Differential SSTL2 Class II (2.5V)
    281
  - SSTL2_II_T_DCI (2.5V) Split-Thevenin Termination
    284
  - SSTL18 Class I (1.8V)
    285
  - Differential SSTL Class I (1.8V)
    286
  - SSTL18 Class II (1.8V)
    288
  - Differential SSTL Class II (1.8V)
    291
  - SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination
    293
  - Differential Termination: DIFF_TERM Attribute
    294
  - LVDS and Extended LVDS (Low Voltage Differential Signaling)
    294
    
    Transmitter Termination
    295
    
    Receiver Termination
    295
  - Hypertransport Protocol (HT)
    296
  - Reduced Swing Differential Signaling (RSDS)
    296
  - BLVDS (Bus LVDS)
    296
  - Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic)
    297
    
    LVPECL Transceiver Termination
    297
- Rules for Combining I/O Standards in the same Bank
  
  298
  - 3.3V I/O Design Guidelines
    302
    
    I/O Standard Design Rules
    302
    
    Mixing Techniques
    304
- Simultaneous Switching Output Limits
  
  305
  - Sparse-Chevron Packages
    305
  - Nominal PCB Specifications
    306
    
    PCB Construction
    306
    
    Signal Return Current Management
    306
    
    Load Traces
    306
    
    Power Distribution System Design
    306
  - Nominal SSO Limit
    307
  - Actual SSO Limits Versus Nominal SSO Limits
    312
  - Electrical Basis of SSO Noise
    312
  - Parasitic Factors Derating Method (PFDM)
    312
  - Weighted Average Calculation of SSO
    314
  - Full Device SSO Calculator
    315
  - Other SSO Assumptions
    315
    
    LVDCI and HSLVDCI Drivers
    315
    
    Bank 0
    315
Chapter 7: Selectio Logic Resources

317
- Introduction
  
  317
- ILOGIC Resources
  
  318
  - Combinatorial Input Path
    319
  - Input DDR Overview (IDDR)
    319
    
    OPPOSITE_EDGE Mode
    319
    
    SAME_EDGE Mode
    319
    
    SAME_EDGE_PIPELINED Mode
    320
  - Input DDR Primitive (IDDR)
    321
  - IDDR VHDL and Verilog Templates
    322
  - ILOGIC Timing Models
    322
    
    ILOGIC Timing Characteristics
    322
    
    ILOGIC Timing Characteristics, DDR
    323
- Input/Output Delay Element (IODELAY)
  
  325
  - IODELAY Primitive
    326
  - IODELAY Ports
    327
  - IODELAY Attributes
    329
  - IODELAY Timing
    330
    
    Stability after an Increment/Decrement Operation
    331
    
    IODELAY VHDL and Verilog Instantiation Template
    331
    
    IODELAY Turnaround Time Usage Model
    332
  - IDELAYCTRL Overview
    337
    
    IDELAYCTRL Primitive
    338
    
    IDELAYCTRL Ports
    338
    
    IDELAYCTRL Timing
    339
    
    IDELAYCTRL Locations
    339
    
    IDELAYCTRL Usage and Design Guidelines
    340
- OLOGIC Resources
  
  344
  - Combinatorial Output Data and 3-State Control Path
    345
  - Output DDR Overview (ODDR)
    345
    
    OPPOSITE_EDGE Mode
    345
    
    SAME_EDGE Mode
    345
    
    Clock Forwarding
    347
  - Output DDR Primitive (ODDR)
    347
  - ODDR VHDL and Verilog Templates
    348
  - OLOGIC Timing Models
    348
    
    Timing Characteristics
    348
Chapter 8 : Advanced Selectio Logic Resources

353
- Introduction
  
  353
- Input Serial-To-Parallel Logic Resources (ISERDES)
  
  353
  - ISERDES Primitive (ISERDES_NODELAY)
    354
  - ISERDES_NODELAY Ports
    355
    
    Registered Outputs - Q1 to Q6
    355
    
    Bitslip Operation - BITSLIP
    356
    
    Clock Enable Inputs - CE1 and CE2
    356
    
    High-Speed Clock Input - CLK
    357
    
    High-Speed Clock Input - CLKB
    357
    
    Divided Clock Input - CLKDIV
    357
    
    Serial Input Data from IOB - D
    357
    
    High-Speed Clock for Strobe-Based Memory Interfaces - OCLK
    357
    
    Reset Input - RST
    357
  - ISERDES_NODELAY Attributes
    358
    
    BITSLIP_ENABLE Attribute
    358
    
    DATA_RATE Attribute
    358
    
    DATA_WIDTH Attribute
    359
    
    INTERFACE_TYPE Attribute
    359
    
    NUM_CE Attribute
    360
    
    SERDES_MODE Attribute
    360
  - ISERDES_NODELAY Clocking Methods
    360
    
    Networking Interface Type
    360
    
    Memory Interface Type
    361
  - ISERDES Width Expansion
    361
    
    Guidelines for Expanding the Serial-To-Parallel Converter Bit Width
    362
  - ISERDES Latencies
    363
  - ISERDES Timing Model and Parameters
    363
    
    Timing Characteristics
    364
    
    Reset Input Timing
    364
  - ISERDES VHDL and Verilog Instantiation Template
    365
  - BITSLIP Submodule
    366
    
    Bitslip Operation
    366
    
    Bitslip Timing Model and Parameters
    368
- Output Parallel-To-Serial Logic Resources (OSERDES)
  
  370
  - Data Parallel-To-Serial Converter
    370
  - 3-State Parallel-To-Serial Conversion
    371
  - OSERDES Primitive
    371
  - OSERDES Ports
    372
    
    Data Path Output - OQ
    372
    
    3-State Control Output - TQ
    372
    
    High-Speed Clock Input - CLK
    372
    
    Divided Clock Input - CLKDIV
    372
    
    Parallel Data Inputs - D1 to D6
    373
    
    Output Data Clock Enable - OCE
    373
    
    Parallel 3-State Inputs - T1 to T4
    373
    
    3-State Signal Clock Enable - TCE
    373
    
    Reset Input - SR
    373
  - OSERDES Attributes
    374
    
    DATA_RATE_OQ Attribute
    374
    
    DATA_RATE_TQ Attribute
    374
    
    DATA_WIDTH Attribute
    375
    
    SERDES_MODE Attribute
    375
    
    TRISTATE_WIDTH Attribute
    375
  - OSERDES Clocking Methods
    375
  - OSERDES Width Expansion
    375
    
    Guidelines for Expanding the Parallel-To-Serial Converter Bit Width
    376
  - OSERDES Latencies
    377
  - OSERDES Timing Model and Parameters
    377
    
    Timing Characteristics of 2:1 SDR Serialization
    378
    
    Timing Characteristics of 8:1 DDR Serialization
    379
    
    Timing Characteristics of 4:1 DDR 3-State Controller Serialization
    380
    
    Reset Output Timing
    381
  - OSERDES VHDL and Verilog Instantiation Templates
    382

Xilinx Virtex-5 FPGA ML561 User Manual (140 pages)

Memory Interfaces Development Board

Brand: Xilinx | Category: Motherboard | Size: 10.07 MB

Revision History
2
Table of Contents
3
Preface: about this Guide

7
- Guide Contents
  
  7
- Additional Documentation
  
  7
- Additional Support Resources
  
  8
- Conventions
  
  9
  - Typographical
    9
  - Online Document
    9
- Terminology
  
  9
Chapter 1: Introduction

11
- About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit
  
  11
- Virtex-5 FPGA ML561 Memory Interfaces Development Board
  
  12
Chapter 2: Getting Started

15
Chapter 3: Hardware Description

17
- Hardware Overview
  
  17
  - Fpga
    18
  - Memories
    19
    
    DDR400 SDRAM Components
    19
    
    Ddr2 DIMM
    19
    
    DDR2 SDRAM Components
    20
    
    Qdrii Sram
    20
    
    RLDRAM II Devices
    20
- Memory Details
  
  21
- External Interfaces
  
  27
  - Usb
    27
  - Rs-232
    27
  - Clocks
    27
    
    200 Mhz LVPECL Clock
    28
    
    SMA Clock
    28
    
    33 Mhz Clock
    28
    
    33 Mhz System ACE Controller Oscillator
    29
    
    GTP Clocks
    29
  - User I/Os
    29
    
    General-Purpose Headers
    29
    
    DIP Switch
    29
    
    Seven-Segment Displays
    30
    
    Light Emitting Diodes (Leds)
    30
    
    Pushbuttons
    30
    
    Power on or off Slide Switch
    31
    
    Soft Touch Probe Points
    31
    
    Power Measurement Header
    31
    
    Liquid Crystal Display Connector
    32
- Power Regulation
  
  33
  - Power Distribution
    33
  - Voltage Regulators
    34
- Board Design Considerations
  
  36
Chapter 4: Electrical Requirements

39
- Power Consumption
  
  39
- FPGA Internal Power Budget
  
  46
Chapter 5: Signal Integrity Recommendations

47
- Termination and Transmission Line Summaries
  
  47
Chapter 6 : Configuration

51
- Configuration Modes
  
  51
- JTAG Chain
  
  52
- JTAG Port
  
  52
- Parallel IV Cable Port
  
  52
- System ACE Interface
  
  52
Chapter 7: ML561 Hardware-Simulation Correlation

55
- Introduction
  
  55
- Test Setup
  
  56
- Signal Integrity Correlation Results
  
  58
  - DDR2 Component Write Operation
    59
  - DDR2 Component Read Operation
    65
  - DDR2 DIMM Write Operation
    70
  - DDR2 DIMM Read Operation
    76
  - QDRII Write Operation
    81
  - QDRII Read Operation
    86
- Summary and Recommendations
  
  91
- How to Generate a User-Specific FPGA IBIS Model
  
  93
Appendix A: FPGA Pinouts

95
- FPGA #1 Pinout
  
  95
- FPGA #2 Pinout
  
  100
- FPGA #3 Pinout
  
  108
Appendix B: Bill of Materials

115
Appendix C: LCD Interface

119
- General
  
  119
- Display Hardware Design
  
  119
- Hardware Schematic Diagram
  
  120
  - Peripheral Device KS0713
    121
    
    Controller - Operation
    123
    
    Controller - LCD Panel Connections
    125
    
    Controller - Power Supply Circuits
    126
  - Operation Example of the 64128EFCBC-3LP
    127
  - Instruction Set
    130
  - Read/Write Characteristics (6800 Mode)
    133
  - Design Examples
    134
    
    LCD Panel Used in Full Graphics Mode
    134
    
    LCD Panel Used in Character Mode
    135
  - Array Connector Numbering
    139

Xilinx Virtex-5 FPGA ML561 User Manual (108 pages)

Brand: Xilinx | Category: Microcontrollers | Size: 3.08 MB

Xilinx Virtex-5 FPGA ML561 User Manual (89 pages)

Networking Interfaces Platform

Brand: Xilinx | Category: Motherboard | Size: 2.54 MB

Table of Contents
3
Preface: about this Guide

7
- Guide Contents
  
  7
- Additional Documentation
  
  7
- Additional Support Resources
  
  8
- Typographical Conventions
  
  9
  - Online Document
    9
Chapter 1: Introduction

11
- About the Virtex-5 FPGA Source-Synchronous Interfaces Tool Kit
  
  11
- Virtex-5 FPGA ML550 Networking Interfaces Development Board
  
  12
Chapter 2: Getting Started

15
- Documentation and Reference Design CD-ROM
  
  15
- Quick Start Guide
  
  15
Chapter 3: Hardware Description

19
- Clock Generation
  
  20
- SDRAM Memory
  
  21
- Liquid Crystal Display
  
  22
  - Display Hardware Design
    23
  - Hardware Schematic Diagrams
    24
- User LED
  
  25
- Configuration INIT and DONE Leds
  
  26
- User Push-Button Switches
  
  26
- Program Switch
  
  27
- USB Port (J22)
  
  27
- LVDS Connectors
  
  28
  - Transmit LVDS
    28
  - Receive LVDS
    28
  - LVDS Loopback Board (Xilinx P/N 0431395)
    29
- Voltage Regulators (TI PTH05000)
  
  29
  - Voltage Regulator ±5% Margin Adjustment (in 2.5% Increments)
    29
    
    Important Note about ± 5% Margin Limits
    31
- Power Monitor Connector
  
  32
- ML550 System Monitor and Power Monitor Support
  
  34
  - ML550 Board System Monitor Support Circuitry Details
    36
    
    5V Input Power Voltage Monitor
    36
    
    VCCAUX Voltage Monitor
    37
    
    VCCO Voltage Monitor
    37
    
    2.5V System Power Voltage Monitor
    38
    
    CCINT Voltage Monitor
    38
    
    Input Power Current Monitor
    39
    
    PCB Temperature Monitor
    39
    
    VREF System Monitor
    40
    
    J19 Mezzanine Board Connector
    41
  - Power Monitor Circuitry
    43
  - Power Monitor Board
    44
  - Data Sheet References
    44
Chapter 4 : Configuration

45
- Configuration Modes
  
  45
- JTAG Chain
  
  46
- JTAG Ports
  
  47
- MM Flat Cable Port
  
  48
- System ACE Interface
  
  49
Appendix A: LVDS

51
- LVDS Transmit Connectors
  
  51
- LVDS Receive Connectors
  
  56
Appendix B: LVDS Loopback Board

61
Appendix C: LCD Interface

63
- General
  
  63
- Display Hardware Design
  
  63
- Hardware Schematic Diagram
  
  64

Xilinx Virtex-5 FPGA ML561 User Manual (88 pages)

Networking Interfaces Platform

Brand: Xilinx | Category: Network Hardware | Size: 2.69 MB

Table of Contents
3
Additional Documentation
7
Guide Contents
7
Preface: about this Guide
7
Additional Support Resources
8
Online Document
9
Typographical Conventions
9
Chapter 1: Introduction

11
- About the Virtex-5 FPGA Source-Synchronous Interfaces Tool Kit
  11
- Virtex-5 FPGA ML550 Networking Interfaces Development Board
  12
Chapter 2: Getting Started

15
Chapter 3: Hardware Description

19
- Clock Generation
  20
- SDRAM Memory
  21
- Liquid Crystal Display
  22
- Display Hardware Design
  23
- Hardware Schematic Diagrams
  24
- User LED
  25
- Configuration INIT and DONE Leds
  26
- User Push-Button Switches
  26
- Program Switch
  27
- USB Port (J22)
  27
- LVDS Connectors
  28
- Transmit LVDS
  28
- Receive LVDS
  28
- LVDS Loopback Board (Xilinx P/N 0431395)
  29
- Voltage Regulators (TI PTH05000)
  29
- Voltage Regulator ±5% Margin Adjustment (in 2.5% Increments)
  29
- Important Note about ± 5% Margin Limits
  31
- Power Monitor Connector
  32
- ML550 System Monitor and Power Monitor Support
  34
- ML550 Board System Monitor Support Circuitry Details
  36
- 5V Input Power Voltage Monitor
  36
- CCAUX Voltage Monitor
  37
- CCO Voltage Monitor
  37
- 2.5V System Power Voltage Monitor
  38
- CCINT Voltage Monitor
  38
- 5V Input Power Current Monitor
  39
- PCB Temperature Monitor
  39
- REF System Monitor
  40
- J19 Mezzanine Board Connector
  41
- Power Monitor Circuitry
  43
- Power Monitor Board
  44
- Data Sheet References
  44
Chapter 4: Configuration

45
- Configuration Modes
  45
- JTAG Chain
  46
- JTAG Ports
  47
- MM Flat Cable Port
  48
- System ACE Interface
  49
Appendix A: LVDS

51
- LVDS Transmit Connectors
  51
- LVDS Receive Connectors
  56
Appendix B: LVDS Loopback Board

61
Appendix C: LCD Interface

63
- General
  63
- Display Hardware Design
  63
- Hardware Schematic Diagram
  64
- Peripheral Device KS0713
  65
- Controller - Operation
  67
- Controller - LCD Panel Connections
  70
- Controller - Power Supply Circuits
  72
- Operation Example of the 64128EFCBC-3LP
  73
- Instruction Set
  76
- Read/Write Characteristics (6800 Mode)
  79
- Design Examples
  80
- LCD Panel Used in Full Graphics Mode
  80
- LCD Panel Used in Character Mode
  81
- Array Connector Numbering
  85
- UCF Information
  85

Xilinx Virtex-5 FPGA ML561 User Manual (28 pages)

RocketIO GTP Transceiver IBIS-AMI Signal Integrity Simulation Kit

Brand: Xilinx | Category: Transceiver | Size: 1.39 MB

Revision History

2
Table of Contents
3
Preface: about this Guide

5
- Guide Contents
  
  5
- Additional Resources
  
  5
Chapter 1: Virtex-5 FPGA GTP Transceiver IBIS-AMI SIS Kit

7
- Introduction
  
  7
- Release Notes for the GTP Transceiver SIS Kit
  
  7
- Installation and Requirements
  
  8
- Kit Overview
  
  8
  - Schematic Sets
    8
  - Transfer Nets
    9
    
    Transfer Net Properties
    9
    
    Transfer Net Usage
    9
  - Libraries
    10
    
    Sisoft Parts
    10
    
    IBIS Files
    10
    
    IBIS-AMI Files
    10
    
    IBIS-AMI Models
    11
    
    Package Models
    11
    
    Channel Models
    11
  - Simulation Environment
    11
  - Clock Domains
    12
  - Bit Sequences
    12
  - Validation Errors/Warnings
    12
- IBIS-AMI Model Control Parameters
  
  12
- Getting Started
  
  13
Appendix A: HSPICE and Quantum Channel Designer/Ibis-AMI Correlation Results

15
- Transmitter Correlation
  
  15
  - Correlation Methodology
    15
  - Correlation Results
    16
    
    Matched (100 Wline) Case Results
    16
    
    Matched (50W and 150 Wline) Case Results
    20
- Receiver Correlation
  
  22
  - Correlation Methodology
    22
  - Correlation Results
    22

Xilinx Categories

Motherboard Computer Hardware Transceiver Microcontrollers Controller

More Xilinx Manuals

Xilinx Virtex-5 FPGA ML561 Manuals

Xilinx Virtex-5 FPGA ML561 User Manual (385 pages)

Table of Contents

Revision History

Preface: about this Guide

Additional Documentation

Additional Support Resources

Typographical Conventions

Chapter 1: Clock Resources

Global and Regional Clocks

Global Clocking Resources

Regional Clocking Resources

VHDL and Verilog Templates

Chapter 2: Clock Management Technology

Clock Management Summary

DCM Summary

DCM Primitives

DCM Ports

DCM Attributes

DCM Design Guidelines

Connecting Dcms to Other Clock Resources in Virtex-5 Devices

Application Examples

VHDL and Verilog Templates, and the Clocking Wizard

DCM Timing Models

Legacy Support

Chapter 3: Phase-Locked Loops (Plls)

Introduction

General Usage Description

Detailed VCO and Output Counter Waveforms

Reference Clock Switching

PLL Use Models

Application Guidelines

PLL in Virtex-4 FPGA PMCD Legacy Mode

Chapter 4: Block RAM

Block RAM Summary

Block RAM Introduction

Synchronous Dual-Port and Single-Port Rams

Additional Block RAM Features in Virtex-5 Devices

Block RAM Library Primitives

Block RAM Port Signals

Block RAM Address Mapping

Block RAM Attributes

Block RAM Initialization in VHDL or Verilog Code

Additional RAMB18 and RAMB36 Primitive Design Considerations

Additional Block RAM Primitives

Block RAM Applications

Block RAM Timing Model

Block RAM Retargeting

Built-In FIFO Support

FIFO Architecture: a Top-Level View

FIFO Primitives

FIFO Port Descriptions

FIFO Operations

FIFO Attributes

FIFO Timing Models and Parameters

FIFO VHDL and Verilog Templates

FIFO Applications

Built-In Error Correction

Legal Block RAM and FIFO Combinations

Chapter 5: Configurable Logic Blocks (Clbs)

CLB Overview

CLB / Slice Timing Models

CLB Primitives

Chapter 6: Selectio Resources

I/O Tile Overview

Selectio Resources Introduction

Selectio Resources General Guidelines

Virtex-5 FPGA Selectio Primitives

Specific Guidelines for I/O Supported Standards

Rules for Combining I/O Standards in the same Bank

Simultaneous Switching Output Limits

Chapter 7: Selectio Logic Resources

Introduction

ILOGIC Resources

Input/Output Delay Element (IODELAY)

OLOGIC Resources

Chapter 8 : Advanced Selectio Logic Resources

Introduction

Input Serial-To-Parallel Logic Resources (ISERDES)

Output Parallel-To-Serial Logic Resources (OSERDES)