Xilinx 7 Series User Manual page 54

Chapter 2: Shared Features
4.
5.
6.
7.
8.
9.
10. The sequence above will simulate correctly if SIM_RESET_SPEEDUP is set to FALSE. If
GTP Transceiver RX Reset in Response to GTRXRESET Pulse
The GTP transceiver allows the user to completely reset the entire GTP transceiver's RX at any time
when needed by sending GTRXRESET an active High pulse. All RX reset attributes listed in
Table 2-18
before applying GTRXRESET. These conditions must be met to use GTRXRESET:
1.
2.
3.
4.
X-Ref Target - Figure 2-20
GTRXRESET
DRP
wr (addr 'h011, bit[11])
DRPRDY
RXPMARESETDONE
RXUSERRDY
RXRESETDONE
RX RESET FSM IDLE
Figure 2-20: GTP Transceiver Receiver Reset after GTRXRESET Pulse
54
Send Feedback
Issue a DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9'h011, set bit[11] to
1'b0.
a. To ensure only bit[11] of DRPADDR 9'h011 is modified, it is best to perform a
read-modify-write function.
Upon DRP write completion, the user can set and hold GTRXRESET Low as desired. The user
can extend the assertion of GTRXRESET, as long as GTRXRESET is held High until the DRP
write is completed.
Note:
It is recommended to use the associated PLLLOCK from either the PLL0 or PLL1 to
release GTRXRESET from High to Low as shown in
Wait for the falling edge of RXPMARESETDONE.
Issue a DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9'h011, restoring the
original setting for bit[11]. The completion of this DRP write must occur before
RXPMARESETDONE switches from Low to High. RXPMARESETDONE stays Low for a
minimum of 0.66 µs.
GTRXRESET should be driven with an output of a register to avoid glitches.
RXPMARESET_TIME should be set to 5'h3. This should be the default setting.
SIM_RESET_SPEEDUP is set to TRUE, the above sequence should be bypassed.
can be set statically or reprogrammed through DRP ports to adjust the required reset time
GTRESETSEL must be driven Low to use sequential mode.
All reset inputs shown on the left of
RXCDRFREQRESET, RXLPMRESET, EYESCANRESET, RXPCSRESET, and
RXBUFRESET must be constantly driven Low during the entire reset process before
RXRESETDONE is detected High.
The associated PLL must indicate locked.
The steps for issuing GTRXRESET is illustrated in
restore setting
1'b0
WAIT RXOSCALWAIT RXPMARESET
RXOSCALRESET RXMPARRESET
_TIME
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Figure 2-19
Figure 2-18 including RXPMARESET, RXCDRRESET,
Figure 2-20
RXMPARRESET
_TIME
RXCDRRESET RXCDRFREQRESET RXLPMRESET RXISCANRESET RXPCSRESET RXBUFRESET
RXCDRFREQRESET
_TIME _TIME
RXCDRPHRESET RXLPMRESET
_TIME
7 Series FPGAs GTP Transceivers User Guide
.
.
RXISCANRESET RXBUFRESET
_TIME _TIME
RXPCSRESET
_TIME _TIME
UG482_c2_120_021113
UG482 (v1.9) December 19, 2016
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