Xilinx 7 Series User Manual page 80

Chapter 3: Transmitter
Similarly,
X-Ref Target - Figure 3-3
Notes relevant to
1.
2.
80
Send Feedback
Figure 3-3 shows the shows the same settings in multiple lanes configuration.
TXOUTCLK
TXUSRCLK2
7 Series FPGAs
GTP Transceiver
TXUSRCLK
TXDATA (TX_DATA_WIDTH =
16 / 20 bits)
TXUSRCLK2
7 Series FPGAs
GTP Transceiver
TXUSRCLK
TXDATA (TX_DATA_WIDTH = 16 / 20 bits)
Figure 3-3: Multiple Lanes—TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode)
Figure 3-3:
BUFH can be used with certain limitations. For details about placement constraints and
restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472, 7 Series
FPGAs Clocking Resources User Guide.
F = F .
TXUSRCLK2 TXUSRCLK
www.xilinx.com
1
BUFG
2
2
2
2
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Design in
FPGA
UG482_c3_03_110911