Chapter 3: Transmitter; Tx Overview - Xilinx 7 Series User Manual

Transmitter

TX Overview

Functional Description
This chapter shows how to configure and use each of the functional blocks inside the transmitter
(TX). Each transceiver includes an independent transmitter, which consists of a PCS and a PMA.
Figure 3-1
into the FPGA TX interface, through the PCS and PMA, and then out the TX driver as high-speed
serial data.
X-Ref Target - Figure 3-1
TX TX
TX
OOB Pre/
Driver
and Post
PCIe Emp
TX Clock
PISO
Dividers
TX Phase
Interpolator
TX PMA
Clock from PLL0 or PLL1
(Near-End PCS Loopback)
The key elements within the GTP transceiver TX are:
1.
2.
3.
4.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows the functional blocks of the transmitter. Parallel data flows from the FPGA logic
Polarity
To RX Parallel Data
Figure 3-1: GTP Transceiver TX Block Diagram
FPGA TX Interface, page 76
TX 8B/10B Encoder, page 83
TX Gearbox, page 86
TX Buffer, page 93
www.xilinx.com
PCIe
Beacon
Pattern
SATA
Generator
OOB
Phase
Adjust
FIFO
From RX Parallel Data
(Far-End PMA Loopback)
Chapter 3
TX
Gearbox
TX PIPE
Control
FPGA
TX
Interface
8B/10B
Encoder
TX Phase
Interpolator
Controller
TX PCS
From RX Parallel Data
(Far-End PCS Loopback)
UG482_c3_01_11281
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