Xilinx 7 Series User Manual page 211

synchronization state machine to the RX gearbox and tells it to slip the data alignment. This process
of slipping and testing the synchronization header repeats until block lock is achieved. When using
the RX gearbox, a block synchronization state machine is required in the FPGA logic.
shows the operation of a block synchronization state machine. The 7 Series FPGAs Transceivers
Wizard has example code for this type of module.
X-Ref Target - Figure 4-57
LOCK_INIT
block_lock <= false
test_sh <= false
Unconditional Transition
RESET_CNT
sh_cnt <= 0
sh_invalid_cnt <= 0
slip_done <= false
test_sh = 1
TEST_SH
test_sh <= false
test_sh = true AND
sh_cnt < 64
sh_valid = 1
VALID_SH
sh_cnt <= sh_cnt + 1
sh_cnt = 64 AND
sh_invalid_cnt = 0
64_GOOD
block_lock <= true
Unconditional Transition
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
sh_valid = 0
sh_cnt = 64 AND
sh_invalid_cnt > 0
Figure 4-57: Block Synchronization State Machine
www.xilinx.com
INVALID_SH
sh_cnt <= sh_cnt + 1
sh_invalid_cnt <= sh_invalid_cnt + 1
sh_cnt = 64 AND
sh_invalid_cnt < 16 AND
block_lock = true
sh_invalid_cnt = 16 OR
block_lock = false
SLIP
block_lock <= false
SLIP <= true
slip_done = true
RX Gearbox
Figure 4-57
test_sh = true AND
sh_cnt < 64 AND
sh_invalid_cnt < 16 AND
block_lock = true
UG482_c4_39_111011
211
Send Feedback