Xilinx 7 Series User Manual page 174

Chapter 4: Receiver
When RX buffer bypass is used, RXSLIDE_MODE cannot be set to AUTO or PMA.
X-Ref Target - Figure 4-35
Clock from
PLL0 or PLL1
RX
Clock
Dividers
RX EQ
RX CDR SIPO
RX OOB
RX Serial
Clock
Ports and Attributes
Table 4-29
Table 4-29: RX Buffer Bypass Ports
RXPHDLYRESET
RXPHALIGN
RXPHALIGNEN
174
Send Feedback
From TX Parallel To TX Parallel
Data (Near-End Data (Far-End
PCS Loopback) PMA Loopback)
Comma
Detect
Polarity
and
Align
PRBS
Checker
After RX phase alignment:
- SPIO parallel clock phase matches RXUSRCLK phase.
- No phase difference between XCLK and RXUSRCLK.
Figure 4-35: Using RX Phase Alignment
defines the RX buffer bypass ports.
Port Dir
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RX PIPE
Control
RX Status
Control
8B/10B
Decoder
Elastic
Buffer
Bypass RX Elastic Buffer
PMA Parallel
Clock
(XCLK)
Clock Domain
In Async RX phase alignment hard reset to force
RXUSRCLK to the center of the delay
alignment tap. The delay alignment tap
has a full range of ±4 ns and a half range
of ±2 ns. This hard reset can be used to
initiate the GTP transceiver to perform
the RX phase and delay alignment
automatically when all other RX buffer
bypass input ports are set Low. It is
recommended to use RXDLYSRESET
only for phase and delay alignment.
In Async Sets the RX phase alignment. Tied Low
when using the auto alignment mode.
In Async RX phase alignment enable. Tied Low
when using the auto alignment mode.
7 Series FPGAs GTP Transceivers User Guide
To TX Parallel
Data (Far-End PCS
Loopback)
FPGA RX
RX
RX
Gear-
box
PCS Parallel FPGA Parallel
Clock
(RXUSRCLK) (RXUSRCLK2)
UG482_c4_24_111011
Description
UG482 (v1.9) December 19, 2016
Interface
Clock