Xilinx 7 Series User Manual page 299

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
006A
4:0
(Cont'd)
15
006B
11:8
006B
2:0
006B
15:0
006F
15:0
0070
15:0
0071
14:8
0075
6:0
0075
14:8
0076
6:0
0076
14:8
0077
6:0
0077
14:8
0078
6:0
0078
14:8
0079
6:0
0079
13:8
007A
5:0
007A
10:8
007C
3
007C
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W TX_CLK25_DIV
R/W PMA_RSV5
R/W PMA_RSV4
R/W TX_DATA_WIDTH
R/W PCS_RSVD_ATTR
R/W PCS_RSVD_ATTR
R/W PCS_RSVD_ATTR
R/W TX_MARGIN_FULL_1
R/W TX_MARGIN_FULL_0
R/W TX_MARGIN_FULL_3
R/W TX_MARGIN_FULL_2
R/W TX_MARGIN_LOW_0
R/W TX_MARGIN_FULL_4
R/W TX_MARGIN_LOW_2
R/W TX_MARGIN_LOW_1
R/W TX_MARGIN_LOW_4
R/W TX_MARGIN_LOW_3
R/W TX_DEEMPH1
R/W TX_DEEMPH0
R/W TX_RXDETECT_REF
R/W TX_MAINCURSOR_SEL
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Attribute Attribute
Bits Encoding
24
25
26
27
4:0 28
29
30
31
32
0 0-1
3:0 0-15
16
20
2:0
32
40
15:0 0-65535
31:16 0-65535
47:32 0-65535
6:0 0-127
6:0 0-127
6:0 0-127
6:0 0-127
6:0 0-127
6:0 0-127
6:0 0-127
6:0 0-127
6:0 0-127
6:0 0-127
5:0 0-63
5:0 0-63
2:0 0-7
0 0-1
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DRP
Encoding
23
24
25
26
27
28
29
30
31
0-1
0-15
2
3
4
5
0-65535
0-65535
0-65535
0-127
0-127
0-127
0-127
0-127
0-127
0-127
0-127
0-127
0-127
0-63
0-63
0-7
0-1
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