User Leds (Active High); User Leds (Active High); User Dip Switches (Active High) And I/O Header; Reference - Xilinx VC7203 User Manual

Chapter 1: VC7203 Board Features and Operation
Table 1-9: SuperClock-2 FPGA I/O Mapping (Cont'd)

User LEDs (Active High)

Callout 23,
DS13 through DS20 are eight active-High LEDs that are connected to user I/O pins on the
FPGA as shown in
purpose determined by the user.
Table 1-10: User LEDs

User DIP Switches (Active High) and I/O Header

Callout 25,
The DIP switch SW2 provides a set of eight active-High switches that are connected to user
I/O pins on the FPGA as shown in
any other purpose determined by the user. Six of the eight I/Os also map to 2 x 6 test
header J125 providing external access for these pins (callout 26,
20
U1 FPGA Pin Net Name
J17 CM_CTRL_23
J20 CM_RST
Figure 1-2.
Table 1-11 These LEDs can be used to indicate status or any other
U1 FPGA Pin Net Name
M37 APP_LED1
M38 APP_LED2
R42 APP_LED3
P42 APP_LED4
N38 APP_LED5
M39 APP_LED6
R40 APP_LED7
P40 APP_LED8
Figure 1-2.
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J82 Pin
107
66

Reference

Designator

DS19
DS20
DS17
DS18
DS16
DS15
DS13
DS14
Table 1-11. These pins can be used to set control pins or
VC7203 GTX Transceiver Characterization Board
Figure 1-2.).
UG957 (v1.0) October 10, 2012