Xilinx 7 Series User Manual page 149

Table 4-17: RX Fabric Clock Output Control Ports (Cont'd)
Port Dir
RXRATEMODE
RXDLYBYPASS
Table 4-18
Table 4-18: RX Fabric Clock Output Control Attributes
Attribute
TRANS_TIME_RATE
RXBUF_RESET_ON_RATE_CHANGE
RXOUT_DIV
Using RXRATE
When users want to change the divider D setting via RXRATE, the steps in
performed:
X-Ref Target - Figure 4-19
RXRATE
RXPMARESETDONE
RXRATEDONE
DRP wr (addr 'h011, bit[11])
DRPRDY
Notes relevant to
1.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Clock Domain
In Async Determines if RXRATE should be treated as synchronous or
asynchronous.
In Async RX delay alignment bypass:
defines the attributes required for RX fabric clock output control.
Type
8-bit Hex
String
Integer
div m
1'b0
Figure 4-19: RXRATE change example
Figure 4-19:
DRP wr denotes the function of performing a DRP write to Addr 9'h011. The exact DRP
transaction is not shown.
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Description
0: Synchronous. When set to 1'b0, an automatic reset sequence
occurs in response to a change on the RXRATE port.
1: Asynchronous.
0: Uses the RX delay alignment circuit. Set to 1'b0 when the RX
buffer is bypassed.
1: Bypasses the RX delay alignment circuit. Set to 1'b1 when the RX
buffer is used.
Description
Reserved. The recommended value from the 7 Series FPGAs
Transceivers Wizard should be used. This attribute determines
when PHYSTATUS and RXRATEDONE are asserted after a rate
change.
When set to TRUE, this attribute enables automatic RX buffer reset
during a rate change event initiated by a change in RXRATE.
This attribute controls the setting for the RX serial clock divider.
This attribute is only valid when RXRATE = 3'b000. Otherwise
the D divider value is controlled by RXRATE. Valid settings are 1,
2, 4, and 8.
div n
RX Fabric Clock Output Control
Figure 4-19 should be
restore setting
UG482_c4_119_020713
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