Xilinx 7 Series User Manual page 73

Interpreting the Digital Monitor Output
This section describes which bits of the DMONITOROUT bus are relevant for the appropriate
selection of DMON_CFG and the manner of interpreting the output.
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7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
unsigned int captureDMON(unsigned int msb, unsigned int lsb);
/////////
/////////////////////////////////////////////////
// Initialize Digital Monitor
/////////////////////////////////////////////////
// Write CFOK_CFG[41] Attribute
drpwrite(0x08B, 0x0490);
// Write DMONITOR_CFG[23:0]
drpwrite(0x087, 0x0000);
drpwrite(0x086, 0x8101);
/////////////////////////////////////////////////
// Read Digital Monitor as often as required
/////////////////////////////////////////////////
while(!done) {
// RXOS
drpwrite(0x0A5, 0x00C2);
captureDMON(6, 0);
/////////////////////////////////////////////////
// LPM Mode Only
/////////////////////////////////////////////////
// LPM Mode Only: RXLPMHF
drpwrite(0x0A5, 0x00C3);
captureDMON(6, 3);
// LPM Mode Only: RXLPMLF
drpwrite(0x0A5, 0x00C4);
captureDMON(6, 3);}
RXLPMOS[6:0] = DMONITOROUT[6:0]
7'd0 = –Full scale
7'd63, 7'd64 = 0
7'd127 = +Full scale
RXLPMHF [3:0] = RXLPMLF [3:0] = DMONITOROUT[6:3]
4'd0 = 0
4'd15 = Full scale
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Digital Monitor
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