Xilinx 7 Series User Manual page 115

Table 3-28: TX Configurable Driver Ports (Cont'd)
Port
TXDIFFCTRL[3:0]
TXELECIDLE
TXINHIBIT
TXMAINCURSOR[6:0]
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Dir Clock Domain
In Async Driver Swing Control. The default is user specified. All listed values are in
mV
PPD
4'b0000
4'b0001
4'b0010
4'b0011
4'b0100
4'b0101
4'b0110
4'b0111
4'b1000
4'b1001
4'b1010
4'b1011
4'b1100
4'b1101
4'b1110
4'b1111
In TXUSRCLK2 When High, this signal forces GTPTXP and GTPTXN both to Common
mode, creating an electrical idle signal.
In TXUSRCLK2 When High, this signal blocks transmission of TXDATA and forces
GTPTXP to 0 and GTPTXN to 1.
In Async Allows the main cursor coefficients to be directly set if the
TX_MAINCURSOR_SEL attribute is set to 1'b1.
51 – TXPOSTCURSOR coefficient units – TXPRECURSOR coefficient units
< TXMAINCURSOR coefficient units
< 80 –TXPOSTCURSOR coefficient units – TXPRECURSOR coefficient units.
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Description
.
[3:0] mV
PPD
253
316
377
439
499
561
621
682
743
799
857
909
959
1002
1043
1074
TX Configurable Driver
115
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