Xilinx 7 Series User Manual page 127

Ports and Attributes
Table 4-1
Table 4-1: RX AFE Ports
GTPRXN,
GTPRXP
PMARSVDOUT1
PMARSVDOUT0
PMARSVDIN2
Table 4-2
Table 4-2: RX AFE Attributes
RX_CM_SEL [1:0]
RX_CM_TRIM [3:0]
TERM_RCAL_CFG[14:0]
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
defines the RX AFE ports.
Port Dir Clock Domain
In (Pad) RX Serial Clock
Out
Out
In
defines the RX AFE attributes.
Attribute Type
2-bit Binary
4-bit Binary
15-bit Binary
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GTPRXN and GTPRXP are differential
complements of one another forming a
differential receiver input pair. These ports
represent pads. The location of these ports
must be constrained (see
page 20) and brought to the top level of the
design.
Async Reserved.
Async Reserved.
Async Reserved.
Description
Controls the mode for the RX termination voltage.
2'b00 - AVTT
2'b01 - GND
2'b10 - Floating
2'b11 - Programmable
Controls the Common mode in Programmable
mode.
4'b0000 – 100 mV
4'b0001 – 200 mV
4'b0010 – 250 mV
4'b0011 – 300 mV
4'b0100 – 350 mV
4'b0101 – 400 mV
4'b0110 – 500 mV
4'b0111 – 550 mV
4'b1000 – 600 mV
4'b1001 – 700 mV
4'b1010 – 800 mV
4'b1011 – 850 mV
4'b1100 – 900 mV
4'b1101 – 950 mV
4'b1110 – 1000 mV
4'b1111 – 1100 mV
Controls the internal termination calibration circuit.
This feature is intended for internal use only.
RX Analog Front End
Description
Implementation,
127
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