Xilinx 7 Series User Manual page 124

Chapter 3: Transmitter
Table 3-32: TX OOB Signaling Ports (Cont'd)
TXPDELECIDLEMODE
TXPD[1:0]
Table 3-33
Table 3-33: TX OOB Signaling Attributes
SATA_PLL_CFG
SATA_BURST_SEQ_LEN
TXOOB_CFG
PCS_RSVD_ATTR[8]
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Port Dir Clock Domain
In
In
shows the OOB signaling attributes.
Attribute Type
2-bit Binary
4-bit Binary
1-bit Binary
1-bit Binary
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TXUSRCLK2 Determines if TXELECIDLE and TXPD
should be treated as synchronous or
asynchronous signals. Enables compliance
during cold and warm PCI Express resets.
1: Asynchronous
0: Synchronous
TXUSRCLK2 Powers down the TX lane according to the
PCI Express encoding.
00: P0 normal operation
01: P0s low recovery time power down
10: P1 longer recovery time, RecDet
still on
11: P2 lowest power state.
Attributes can control the transition times
between these power down mode
(PD_TRANS_TIME_FROM_P2,
PD_TRANS_TIME_NONE_P2,
PD_TRANS_TIME_TO_P2).
Configuration bits for the PLL setting related to
SAS/SATA.
Number of bursts in a COM sequence for SAS/
SATA.
TX OOB configuration.
OOB Powerdown
1'b0 - circuit powered down
1'b1 - Circuit powered up (PCIe, SATA/
SAS, protocols/applications using OOB)
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Description
Description