Xilinx 7 Series User Manual page 227

LVPECL
See
X-Ref Target - Figure 5-9
LVPECL
Oscillator
Figure 5-9: Interfacing LVPECL Oscillator to Artix-7 FPGA GTP Reference Clock Input
Notes relative to
1.
AC Coupled Reference Clock
AC coupling of the oscillator reference clock output to the GTP Quad reference clock inputs serves
multiple purposes:
•
•
•
To minimize noise and power consumption, external AC coupling capacitors between the sourcing
oscillator and the GTP Quad dedicated clock reference clock input pins are required.
Unused Reference Clocks
It is recommended to leave the unused differential input pin clock pair floating (both
MGTREFCLKP and MGTREFCLKN).
Reference Clock Power
The GTP reference clock input circuit is powered by MGTAVCC. Excessive noise on this supply
will have a negative impact on the performance of any GTP Quad that uses the reference clock from
this circuit.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Figure 5-9.
0.1µF
Ω
(1)
240
Ω
(1)
240
0.1µF
Figure 5-9:
Nominal values. Refer to the oscillator vendor data sheet for actual bias resistor requirement.
Blocking a DC current between the oscillator and the GTP Quad dedicated clock input pins
(which reduces the power consumption of both parts as well).
Common mode voltage independence.
The AC coupling capacitor forms a high-pass filter with the on-chip termination that attenuates
a wander of the reference clock.
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Reference Clock
Internal to Artix-7 FPGA
GTP Reference Clock
Input Buffer
UG482_c5_09_080612
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