Xilinx 7 Series User Manual page 28

Chapter 2: Shared Features
Table 2-4: GTPE2_COMMON Clocking Ports (Cont'd)
GTWESTREFCLK1
GTEASTREFCLK0
GTEASTREFCLK1
PLL0OUTCLK
PLL1OUTCLK
PLL0OUTREFCLK
PLL1OUTREFCLK
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Port Direction
In
In
In
Out
Out
Out
Out
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Clock
Description
Domain
Clock West-bound clock from the Quad on the right
side of the device.
Clock East-bound clock from the Quad on the left side
of the device.
Clock East-bound clock from the Quad on the left side
of the device.
Clock PLL0 clock output. The user must connect this
port to the PLL0CLK port on the
GTPE2_CHANNEL primitive.
Clock PLL1 clock output. The user must connect this
port to the PLL1CLK port on the
GTPE2_CHANNEL primitive.
Clock The user must connect this port to the
PLL0REFCLK port on the GTPE2_CHANNEL
primitive.
Clock The user must connect this port to the
PLL1REFCLK port on the GTPE2_CHANNEL
primitive.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016