Xilinx 7 Series User Manual page 43

Table 2-14: TX Initialization and Reset Ports (Cont'd)
TXPCSRESET
TXUSERRDY
TXRESETDONE
TXPMARESETD
ONE
CFGRESET
PCSRSVDOUT
Table 2-15
reset time required by the TX PMA or the TX PCS varies depending on line rate. The factor
affecting PMA reset time and PCS reset time are user-configurable attributes
TXPMARESET_TIME and TXPCSRESET_TIME.
Table 2-15: TX Initialization and Reset Attributes
TXPMARESET_TIME
TXPCSRESET_TIME
GTP Transceiver TX Reset in Response to Completion of Configuration
The TX reset sequence shown in
must meet these conditions:
1.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Port Dir
In
In
Out
Out
In
Out
lists attributes required by the GTP transceiver's TX initialization. In general cases, the
Attribute Type
5-bit Binary
5-bit Binary
GTRESETSEL must be Low to use sequential mode.
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Clock Domain
Async This port is used to reset the TX PCS. It is driven
High and then deasserted to start the PCS reset
process. In sequential mode, activating this port
only resets the TX PCS.
Async This port is driven High from the user's
application when TXUSRCLK and
TXUSRCLK2 are stable. For example, if an
MMCM is used to generate both TXUSRCLK
and TXUSRCLK2, then the MMCM lock signal
can be used here.
TXUSRCLK2 This active-High signal indicates the GTP
transceiver TX has finished reset and is ready
for use. This port is driven Low when
GTTXRESET goes High and is not driven High
until the GTP transceiver TX detects
TXUSERRDY High.
Async This active-High signal indicates GTP TX PMA
reset is complete. This port is driven Low when
GTTXRESET or TXPMARESET is asserted.
Async Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used.
Async Reserved.
Reserved. Represents the time duration to apply a TX
PMA reset. The recommended value from the 7 Series
FPGAs Transceivers Wizard should be used. Must be a
non-zero value when GTTXRESET or TXPMARESET is
used to initiate the reset process.
Reserved. Represents the time duration to apply a TX
PCS reset. The recommended value from the 7 Series
FPGAs Transceivers Wizard should be used. Must be a
non-zero value when TXPCSRESET is used to initiate
the reset process.
Figure 2-13 is not automatically started to follow global GSR. It
Reset and Initialization
Description
Description
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