Xilinx 7 Series User Manual page 77

Fpgas gtp transceivers
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Table 3-2: TX Data Transmitted when 8B/10B Encoder Bypassed
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Data
Transmitted
TXUSRCLK and TXUSRCLK2 Generation
The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2.
TXUSRCLK is the internal clock for the PCS logic in the GTP transceiver transmitter. The required
rate for TXUSRCLK depends on the internal datapath width of the GTPE2_CHANNEL primitive
and the TX line rate of the GTP transceiver transmitter.
required rate for TXUSRCLK.
TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTP
transceiver. Most signals into the TX side of the GTP transceiver are sampled on the positive edge
of TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a fixed-rate relationship based on the
TX_DATA_WIDTH setting.
TXUSRCLK per TX_DATA_WIDTH value.
Table 3-3: TXUSRCLK2 Frequency Relationship to TXUSRCLK
These rules about the relationships between clocks must be observed for TXUSRCLK and
TXUSRCLK2:
Ports and Attributes
Table 3-4
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
< < < Data Transmission Order is Right to Left (LSB to MSB) < < <
TXUSRCLK Rate
Table 3-3
FPGA Interface Width
2-Byte
4-Byte
TXUSRCLK and TXUSRCLK2 must be positive-edge aligned, with as little skew as possible
between them. As a result, low-skew clock resources (BUFGs and BUFHs) should be used to
drive TXUSRCLK and TXUSRCLK2.
Even though they might run at different frequencies, TXUSRCLK, TXUSRCLK2, and the
transmitter reference clock must have the same oscillator as their source. Thus TXUSRCLK
and TXUSRCLK2 must be multiplied or divided versions of the transmitter reference clock.
defines the FPGA TX Interface ports.
www.xilinx.com
Equation 3-1
Line Rate
=
------------------------------------------------------------------ -
Internal Datapath Width
shows the relationship between TXUSRCLK2 and
TX_DATA_WIDTH
TXUSRCLK2 Frequency
16, 20
F
32, 40
F
TXUSRCLK2
FPGA TX Interface
8
7
6
5
4
3
shows how to calculate the
Equation 3-1
= F
TXUSRCLK2
TXUSRCLK
= F
/2
TXUSRCLK
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