Xilinx 7 Series User Manual page 47

After Power-up and Configuration
The entire GTP TX requires a reset after configuration. See
to Completion of Configuration
After Turning on a Reference Clock to the PLL Being Used
If the reference clock(s) changes or the GTP transceiver(s) are powered up after configuration,
GTTXRESET should be toggled after the PLL fully completes its reset procedure.
After Changing the Reference Clock to the PLL Being Used
Whenever the reference clock input to the PLL is changed, the PLL must be reset afterwards to
ensure that it locks to the new frequency. The GTTXRESET should be toggled after the PLL fully
completes its reset procedure.
After Assertion/Deassertion of PLL[0/1]PD, for the PLL Being Used
When the PLL being used goes back to normal operation after power down, the PLL must be reset.
The GTTXRESET should be toggled after the PLL fully completes its reset procedure.
After Assertion/Deassertion of TXPD[1:0]
After the TXPD signal is deasserted, GTTXRESET must be toggled.
TX Rate Change
When a rate change is performed using the TXRATE port and TXRATEMODE is set to 1'b0, the
required reset sequence is performed automatically. When TXRATEDONE is asserted, it indicates
that both the rate change and the necessary reset sequence have been applied and completed.
If the TX buffer is enabled, the TXBUF_RESET_ON_RATE_CHANGE attribute should be set to
TRUE to allow the TX buffer to reset automatically after the rate change.
If TX buffer bypass mode is used, alignment must be repeated after TXRATEDONE is asserted.
TX Parallel Clock Source Reset
The clocks driving TXUSRCLK and TXUSRCLK2 must be stable for correct operation.
These clocks are often driven from an MMCM in the FPGA to meet phase and frequency
requirements. If the MMCM loses lock and begins producing incorrect output, TXPCSRESET
should be toggled after the clock source re-locks.
If TX buffer bypass mode is used, alignment must be repeated after the completion of the reset
procedure.
RX Initialization and Reset
The GTP transceiver's RX uses a reset state machine to control the reset process. Due to its
complexity, the GTP transceiver's RX is partitioned into more reset regions than the GTP
transceiver's TX. The partition allows RX initialization and reset to be operated in either sequential
mode or single mode as shown in
1.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
for the procedure.
RX in Sequential Mode
To initialize the GTP transceiver's RX, GTRXRESET must be used in sequential mode.
Activating the GTRXRESET input can automatically trigger a full asynchronous RX reset. The
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GTP Transceiver TX Reset in Response
Figure 2-18:
Reset and Initialization
47
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