Chapter 3: Clocking And Clock Domains; Clock Domain Architecture; Figure 3-1: Reference Clock Selection; Reference Clocks - Xilinx RocketIO X User Manual

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Clocking and Clock Domains

Clock Domain Architecture

There are seven clock inputs into each RocketIO X transceiver instantiation. REFCLK,
REFCLK2, and BREFCLK are clocks generated from an external source. BREFCLK is a set
of differential inputs into the FPGA that can create a clock tree for all MGTs on one side of
the device. See
BREFCLK of the RocketIO X Multi-Gigabit Transceiver (MGT). While only one of these
reference clocks is needed to drive the MGT, BREFCLK inputs for the reference clock are
recommended for the best operation. All characterization and data sheet numbers use the
BREFCLK. Therefore, REFCLK usage results in performance degradation from the
published performance numbers. BREFCLK also clocks a Digital Clock Manager (DCM) to
generate all of the other clocks for the MGT.
Note:
without the use of a DCM.
Note:
x
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
Figure 3-1. The reference clocks connect to the REFCLK, REFCLK2, or
Do not run a reference clock through a DCM; jitter control is optimized on reference clock nets
BREFCLK inputs can only be used to drive the MGTs and DCMs.
REFCLKBSEL
REFCLKSEL
From
REFCLK
FPGA
Fabric
REFCLK2
BREFCLKPIN
BREFCLKNIN

Figure 3-1: Reference Clock Selection

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