Xilinx 7 Series User Manual page 72

Chapter 2: Shared Features
Use Mode
Reading loop values out of the digital monitor requires a clock on input clock port
DMONITORCLK, change adaptation loop select through DRP, and monitor output
DMONITOROUT. Set the DMONITOR_CFG attribute via the DRP port to the appropriate loop for
monitoring. The DRP location of DMONITOR_CFG is:
The output can be observed on DMONITOROUT. The signals from the digital monitor are LSB
aligned and asynchronous.
Capturing the Digital Monitor Output
The DMONITOROUT signals change slowly in comparison to the RXUSRCLK2s. One way to
capture the DMONITOROUT is described here.
Any method that captures the information successfully is valid.
Capturing the Digital Monitor Output Through Software
The dmonitorout_sync described in the Verilog code in the section above can be mapped into host
processor memory to capture the digital monitor output. The channel DRP port can be mapped into
host processor memory to select the adaptation loop to be monitored.
The following example C code is provided as an illustration. The drpread and drpwrite functions are
DRP operations described in
dmonitorout_sync register described in the above Verilog code.
72
Send Feedback
0x086[15:0] = DMONITOR_CFG[15:0]
0x087[7:0] = DMONITOR_CFG[23:16]
reg [7:0] compare1, compare2, dmonitorout_sync;
always@ (posedge RXUSRCLK2)
begin
if (reset)
begin
compare1 <= 8'd0;
compare2 <= 8'd0;
dmonitorout_sync <= 8'd0;
end
else
begin
compare1 <= DMONITOROUT;
compare2 <= compare1;
if (compare1 == compare2)
dmonitorout_sync <= compare2;
else
dmonitorout_sync<=dmonitorout_sync;
end //else
end //always
Usage Model, page
//////////////////////////////////////////
// Function Prototypes
//////////////////////////////////////////
void drpwrite(unsigned int drpaddress, unsigned int drpvalue);
usigned int drpread(unsigned int drpaddress);
www.xilinx.com
69. The captureDMON function reads
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016