Xilinx 7 Series User Manual page 53

GTP Transceiver RX Reset in Response to Completion of Configuration
The RX reset sequence shown in
These conditions must be met:
1.
2.
3.
4.
If the reset mode is defaulted to sequential mode upon configuration, then PLL[0/1]RESET and
GTRXRESET can be asserted after waiting for a minimum of 500 ns after configuration is
complete.
If the reset mode is defaulted to single mode, then the user must:
1.
2.
3.
When users want to issue an GTRXRESET upon configuration, the steps in
performed.
X-Ref Target - Figure 2-19
PLL0RESET/
PLL1RESET
PLL0LOCK/
PLL1LOCK
GTRXRESET
DRP
(wr addr 'h011, bit[11])
DRPRDY
RXPMARESETDONE
RXUSERRDY
RXRESETDONE
TX RESET FSM IDLE
Figure 2-19: GTP Transceiver Receiver after FPGA Configuration
Notes relevant to
1.
2.
3.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
GTRESETSEL must be driven Low to use the sequential mode.
GTRXRESET must be used.
All single reset inputs including RXPMARESET, RXCDRRESET, RXCDRFREQRESET,
RXLPMRESET, EYESCANRESET, RXPCSRESET, and RXBUFRESET must be constantly
held Low during the entire reset process before RXRESETDONE goes High.
GTRXRESET cannot be driven Low until the associated PLL is locked.
Wait a minimum of 500 ns after configuration is complete.
Change reset mode to Sequential mode.
Wait another 300-500 ns.
1'b0 restore setting
WAIT RXOSCALRESET RXOSCALWAIT RXPMARESET
RXPMARESET
RXOSCALRESET
_TIME
Figure 2-19:
"DRP wr" denotes the function of performing a DRP write to addr 9'h011. The exact DRP
transaction is not shown.
The sequence of events in Figure 2-19
When the user wants to trigger RX reset upon configuration, assert and release
PLL[0/1]RESET while GTRXRESET is kept asserted. The assertion of GTRXRESET causes
RXPMARESETDONE to go Low.
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Figure 2-18 is not automatically started following the global GSR.
RXCDRRESET RXCDRFREQRESET RXLPMRESET RXISCANRESET RXPCSRESET RXBUFRESET
RXPCDRFREQRESET
_TIME
_TIME
RXLPMRESET
RXPCDRPHRESET
_TIME
is not drawn to scale.
Reset and Initialization
Figure 2-19 should be
RXBUFRESET
RXISCANRESET
_TIME
_TIME
RXPCSRESET
_TIME _TIME
UG482_c2_119_021113
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