Fgg484 Package Placement Diagram - Xilinx 7 Series User Manual

FGG484 Package Placement Diagram

Figure A-4
X-Ref Target - Figure A-4
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
and shows the placement diagram for the FGG484 package.
XC7A15T:GTPE2_CHANNEL_X0Y3
XC7A35T:GTPE2_CHANNEL_X0Y3
XC7A50T:GTPE2_CHANNEL_X0Y3
XC7A75T:GTPE2_CHANNEL_X0Y7
XC7A100T:GTPE2_CHANNEL_X0Y7
XC7A15T:GTPE2_CHANNEL_X0Y2
XC7A35T:GTPE2_CHANNEL_X0Y2
XC7A50T:GTPE2_CHANNEL_X0Y2
XC7A75T:GTPE2_CHANNEL_X0Y6
XC7A100T:GTPE2_CHANNEL_X0Y6
XC7A15T:GTPE2_COMMON_X0Y0
XC7A35T:GTPE2_COMMON_X0Y0
XC7A50T:GTPE2_COMMON_X0Y0
XC7A75T:GTPE2_COMMON_X0Y1
XC7A100T:GTPE2_COMMON_X0Y1
XC7A15T:GTPE2_CHANNEL_X0Y1
XC7A35T:GTPE2_CHANNEL_X0Y1
XC7A50T:GTPE2_CHANNEL_X0Y1
XC7A75T:GTPE2_CHANNEL_X0Y5
XC7A100T:GTPE2_CHANNEL_X0Y5
XC7A15T:GTPE2_CHANNEL_X0Y0
XC7A35T:GTPE2_CHANNEL_X0Y0
XC7A50T:GTPE2_CHANNEL_X0Y0
XC7A75T:GTPE2_CHANNEL_X0Y4
XC7A100T:GTPE2_CHANNEL_X0Y4
Figure A-4: Placement Diagram for the FGG484 Package
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FGG484 Package Placement Diagram
D7 MGTPTXP3_216
C7 MGTPTXN3_216
D9 MGTPRXP3_216
C9 MGTPRXN3_216
B6 MGTPTXP2_216
A6 MGTPTXN2_216
B10 MGTPRXP2_216
A10 MGTPRXN2_216
F10 MGTREFCLK1P_216
E10 MGTREFCLK1N_216
F6 MGTREFCLK0P_216
E6 MGTREFCLK0N_216
D5 MGTPTXP1_216
C5 MGTPTXN1_216
D11 MGTPRXP1_216
C11 MGTPRXN1_216
B4 MGTPTXP0_216
A4 MGTPTXN0_216
B8 MGTPRXP0_216
A8 MGTPRXN0_216
UG482_aA_01_110514
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