Xilinx 7 Series User Manual page 81

TXOUTCLK Driving GTP Transceiver TX in 4-Byte Mode
In
32 or 40). The frequency of TXUSRCLK2 is equal to half of the frequency of TXUSRCLK.
MMCMs or PLLs, which are part of the clock management tiles (CMTs) located in the top half of
the device, can only drive the BUFGs in the top half of the devices. Similarly, MMCMs or PLLs
located in the bottom half can only drive BUFGs in the bottom half.
X-Ref Target - Figure 3-4
Notes relevant to
1.
2.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Figure 3-4, TXOUTCLK is used to drive TXUSRCLK2 for 4-byte mode (TX_DATA_WIDTH =
TXOUTCLK
TXUSRCLK2
7 Series FPGAs
GTP Transceiver
TXUSRCLK
Figure 3-4: Single Lane—TXOUTCLK Drives TXUSRCLK2 (4-Byte Mode)
Figure 3-4:
F = F
TXUSRCLK2 TXUSRCLK
In the XC7A200T device, BUFH can be used with certain limitations. For details about
placement constraints and restrictions on clocking resources (MMCM, BUFH, BUFG, etc.),
refer to UG472, 7 Series FPGAs Clocking Resources User Guide.
www.xilinx.com
MMCME2
or
PLLE2
BUFG
or BUFH
CLKIN
1
1
TXDATA (32 / 40 bits)
/2
FPGA TX Interface
LOCKED
2
BUFG
CLKOUT0
CLKOUT1
2
BUFG
Design in
FPGA
UG482_c3_04_041012
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