Xilinx 7 Series User Manual page 69

Usage Model
Write Operation
Figure 2-23
DRPRDY is asserted.
X-Ref Target - Figure 2-23
DRPADDR
Read Operation
Figure 2-24
DRPRDY is asserted.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows the DRP write operation timing. New DRP operation can be initiated when
DRPCLK
DRPEN
DRPRDY
DRPWE
ADR
DAT
DRPDI
DRPDO
(1) After a DRP write is requested, it takes 5 DRPCLK clock cycles
for the DRPRDY signal to be asserted.
shows the DRP read operation timing. New DRP operation can be initiated when
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Figure 2-23: DRP Write Timing
Dynamic Reconfiguration Port
(1)
UG482_c2_12_040213
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