Tx Configurable Driver - Xilinx 7 Series User Manual

Chapter 3: Transmitter

TX Configurable Driver

Functional Description
The GTP transceiver TX driver is a high-speed current-mode differential output buffer. To
maximize signal integrity, it includes these features:
•
•
•
X-Ref Target - Figure 3-21
TX Serial Clock=
Ports and Attributes
Table 3-28
Table 3-28: TX Configurable Driver Ports
Port
TXBUFDIFFCTRL[2:0]
TXDEEMPH
114
Send Feedback
Differential voltage control
Pre-cursor and post-cursor transmit pre-emphasis
Calibrated termination resistors
PISO
Data Rate/2
Figure 3-21: TX Configurable Driver Block Diagram
defines the TX configurable driver ports.
Dir Clock Domain
In Async Pre-driver Swing Control. The default is 3'b100 (nominal value).
Do not modify this value.
In TXUSRCLK2 TX de-emphasis control for PCI Express PIPE 2.0 interface. This signal is
mapped internally to TXPOSTCURSOR via attributes.
0: 6.0 dB de-emphasis (TX_DEEMPH_0[4:0] attribute)
1: 3.5 dB de-emphasis (TX_DEEMPH_1[4:0] attribute)
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Pre-Emphasis
Pre-Driver
Pad Driver
TXPRECURSOR[4:0]
Main
Pre-Driver
Pad Driver
TXDIFFCTRL[3:0]
Post-Emphasis
Pre-Driver
Pad Driver
TXPOSTCURSOR[4:0]
Description
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
MGTAVTT
50 50
TXP
TXN
UG482_c3_20_110911