Xilinx 7 Series User Manual page 154

Chapter 4: Receiver
Ports and Attributes
Table 4-19
Table 4-19: RX Margin Analysis Ports
EYESCANDATAERROR
EYESCANTRIGGER
RXRATE
Table 4-20
Table 4-20: RX Margin Analysis Attributes
Attribute
ES_VERT_OFFSET
Binary
ES_HORZ_OFFSET
ES_PRESCALE
Binary
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defines ports related to the RX eye scan function.
Port
defines RX eye scan attributes. Lower case attribute names indicate R/O.
Type
9-bit Controls the vertical (differential voltage) offset of the scan sample:
[6:0]: Offset magnitude.
[7]: Offset sign (1 is negative, 0 is positive).
Controls the horizontal (phase) offset of the scan sample.
12-bit
Hex
[10:0]: Phase offset (two's complement). The center of data eye (0 UI) corresponds to a count
of 11'd0 for all data rates. The table below lists the minimum count (representing -0.5 UI)
and maximum count (representing +0.5 UI) for each data rate.
Rate min count [dec(bin)]
Full -32 (11'b11111100000)
Half -64 (11'b11111000000)
Qrtr -128 (11'b11110000000)
Octal -256 (11'b11100000000)
[11]: Phase unification. Must be set to 0 for all positive counts (including zero) and to 1 for all
negative counts.
5-bit Controls the pre-scaling of the sample count to keep both sample count and error count in
reasonable precision within the 16-bit register range. Prescale = 2
(1+0)
prescale is 2 = 2 and maximum prescale is 2
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Dir Domain
Out async Asserts high for one REC_CLK cycle when
an (unmasked) error occurs while in the
COUNT or ARMED state.
In RXUSRCLK2 Causes a trigger event.
See ES_CONTROL[4] below.
In RXUSRCLK2 This port dynamically controls the setting for
the RX serial clock divider D (see
and it is used with RXOUT_DIV attribute.
3'b000: Use RXOUT_DIV divider value
3'b001: Set D divider to 1
3'b010: Set D divider to 2
3'b011: Set D divider to 4
3'b100: Set D divider to 8
Description
eye center [dec(bin)]
+0(11'b00000000000)
+0(11'b00000000000)
+0(11'b00000000000)
+0(11'b00000000000)
(1+31)
7 Series FPGAs GTP Transceivers User Guide
Description
Table
max count [dec(bin)]
+32(11'b00000100000)
+64(11'b00001000000)
+128(11'b00010000000)
+256(11'b00100000000)
(1 + register value)
, so minimum
= 4,284,967,296.
UG482 (v1.9) December 19, 2016
4-16)