Fpga Tx Interface - Xilinx 7 Series User Manual

Chapter 3: Transmitter
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FPGA TX Interface

Functional Description
The FPGA TX interface is the FPGA's gateway to the TX datapath of the GTP transceiver.
Applications transmit data through the GTP transceiver by writing data to the TXDATA port on the
positive edge of TXUSRCLK2. The width of the port can be configured to be two or four bytes
wide. The actual width of the port depends on the TX_DATA_WIDTH attribute and TX8B10BEN
port setting. Port widths can be 16, 20, 32, and 40 bits. The rate of the parallel clock (TXUSRCLK2)
at the interface is determined by the TX line rate, the width of the TXDATA port, and whether or not
8B/10B encoding is enabled. A second parallel clock (TXUSRCLK) must be provided for the
internal PCS logic in the transmitter. This section shows how to drive the parallel clocks and
explains the constraints on those clocks for correct operation.
Interface Width Configuration
The 7 series FPGA GTP transceiver contains a 2-byte internal datapath. The FPGA interface width
is configurable by setting the TX_DATA_WIDTH attribute. When the 8B/10B encoder is enabled,
the TX_DATA_WIDTH attribute must be configured to 20 bits or 40 bits, and in this case, the FPGA
TX interface only uses the TXDATA ports. For example, TXDATA[15:0] is used when the FPGA
interface width is 16. When the 8B/10B encoder is bypassed, the TX_DATA_WIDTH attribute can
be configured to any of the available widths: 16, 20, 32, or 40 bits.
Table 3-1
described in more detail in
Table 3-1: FPGA TX Interface Datapath Configuration
When the 8B/10B encoder is bypassed and the TX_DATA_WIDTH is 20 or 40, the
TXCHARDISPMODE and TXCHARDISPVAL ports are used to extend the TXDATA port from 16
to 20 bits, or 32 to 40 bits.
disabled. When the TX gearbox is used, refer to
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Send Feedback
TX Pattern Generator, page 103
TX Pattern Generator, page 103
TX Polarity Control, page 106
TX Fabric Clock Output Control, page 107
TX Configurable Driver, page 114
TX Receiver Detect Support for PCI Express Designs, page 121
TX Out-of-Band Signaling, page 123
shows how the interface width for the TX datapath is selected. 8B/10B encoding is
TX 8B/10B Encoder, page
TX8B10BEN TX_DATA_WIDTH
1 20
40
0 16
20
32
40
Table 3-2
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FPGA Interface Internal Data
Width Width
16 20
32 20
16 16
20 20
32 16
40 20
shows the data transmitted when the 8B/10B encoder is
TX Gearbox, page 86
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
for data transmission order.