Xilinx 7 Series User Manual page 82

Chapter 3: Transmitter
Similarly,
X-Ref Target - Figure 3-5
Notes relevant to
1.
2.
82
Send Feedback
Figure 3-5 shows the shows the same settings in multiple lanes configuration.
TXOUTCLK
TXUSRCLK2
Artix-7 FPGA
GTP Transceiver
TXUSRCLK
TXDATA (TX_DATA_WIDTH = 32 / 40 bits)
TXUSRCLK2
Artix-7 FPGA
GTP Transceiver
TXUSRCLK
TXDATA (TX_DATA_WIDTH = 32 / 40 bits)
Figure 3-5: Multiple Lanes—TXOUTCLK Drives TXUSRCLK2 (4-Byte Mode)
Figure 3-5:
F = F /2.
TXUSRCLK2 TXUSRCLK
In the XC7A200T device, BUFH can be used with certain limitations. For details about
placement constraints and restrictions on clocking resources (MMCM, BUFH, BUFG, etc.),
refer to UG472, 7 Series FPGAs Clocking Resources User Guide.
www.xilinx.com
CLKOUT0
MMCME2
CLKOUT1
or
BUFG
PLLE2
or BUFH
LOCKED
CLKIN
1
1
Design in
FPGA
1
1
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
2
BUFG
2
BUFG
UG482_c3_05_041012