Xilinx 7 Series User Manual page 178

Chapter 4: Receiver
Table 4-30: RX Buffer Bypass Attributes (Cont'd)
RXSYNC_OVRD
TST_RSV[0]
RX Buffer Bypass Use Modes
RX phase alignment can be performed on one channel (single lane) or a group of channels sharing
a single RXOUTCLK (multi-lane). For GTP transceivers, RX buffer bypass supports single-lane
auto mode, and multi-lane applications in manual and auto mode
Table 4-31: RX Buffer Bypass Use Modes
Using RX Buffer Bypass in Single-Lane Auto Mode
These GTP transceiver settings should be used to bypass the RX buffer:
•
•
•
•
With the RX recovered clock selected, RXOUTCLK is to be used as the source of RXUSRCLK.
The user must ensure that RXOUTCLK and the selected RX recovered clock are running and
operating at the desired frequency. When the RX elastic buffer is bypassed, the RX phase alignment
procedure must be performed after these conditions:
•
•
•
•
To set up RX buffer bypass in single-lane auto mode, these attributes should be set:
•
•
Set the ports as per
178
Send Feedback
Attribute
Rx Buffer Bypass GTP Transceiver
Single-Lane
Multi-Lane
RXBUF_EN = FALSE.
RX_XCLK_SEL = RXUSR.
RXOUTCLKSEL = 010b to select the RX recovered clock as the source of RXOUTCLK.
RXDDIEN = 1.
Resetting or powering up the GTP receiver.
Resetting or powering up the PLL.
Changing the RX recovered clock source or frequency.
Changing the GTP RX line rate.
RXSYNC_MULTILANE = 0
RXSYNC_OVRD = 0
Figure 4-36.
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Type
1-bit Binary Manual mode override.
0: RX Buffer bypass auto mode is enabled.
1: RX Buffer bypass manual mode is used. RX
Buffer bypass control is implemented in fabric
logic.
1-bit Binary 0: Normal.
1: Override data delay insertion (DDI) delay
setting with RX_DDI_SEL attribute.
Auto
Manual or Auto
7 Series FPGAs GTP Transceivers User Guide
Description
(Table 4-31).
UG482 (v1.9) December 19, 2016