Input-Data Register (Sidr0-3), Output-Data Register (Sodr0-3) - Fujitsu MB91150 Series Hardware Manual

CHAPTER 15 UART
15.4.4 Input-data register (SIDR0-3), output-data register
(SODR0-3)
The input-data register (SIDR0-3) is for receiving serial data. The output-data register
(SODR0-3) is for sending serial data. The SIDR0-3 and SODR0-3 registers are located
at the same address.
I Input-data register (SIDR0-3)
The configuration of the input-data register (SIDR0-3) as shown below.
Address
ch0:0000_001Dh
ch1:0000_0021h
ch2:0000_0025h
ch3:0000_0029h
R: Read only
X: Undetermined
Received data is stored in this register. The shift register converts the serial data signal sent to
the SIN0-3 pins. The converted data is stored in this register. When the data length is 7 bits, the
high-order bit (D7) contains invalid data. When the receive data is stored in this register, the
receive data full flag bit (SSR0-3: RDRF) is set to 1. If receive-interrupt request is enabled, a
receive interrupt occurs.
Read the SIDR0-3 when the RDRF bit of the status register (SSR0-3) is 1. The RDRF bit is
automatically cleared to 0 when the SIDR0-3 is read. If a receive error occurs (SSR0-3: If PE,
ORE, or FRE is 1), the SIDR0-3 data becomes invalid.
I Output-data register (SODR0-3)
The configuration of the output-data register (SODR0-3) is shown below.
Address
ch0:0000_001Dh
ch1:0000_0021h
ch2:0000_0025h
ch3:0000_0029h
R: Read only
X: Undetermined
When send data is written to this register in send-enabled status, the send data is transferred to
the send-shift register, is converted into serial data, and is sent out from the serial data output
pins (SOT0-3 pins). When the data length is 7 bits, the high-order bit (D7) contains invalid data.
When the send data is written to this register, the send data empty flag (SSR0-3: TDRE) is
cleared to 0. When the transfer to the send-shift register terminates, the flag is set to 1. When
318
bit15 ........... bit8 bit7
D7
R
bit15 ................ bit8 bit7
D7
W
bit6 bit5 bit4 bit3
D6 D5 D4 D3
R R R
bit6 bit5 bit4 bit3
D6 D5 D4 D3
W W W
bit2 bit1 bit0
D2 D1 D0
R R R R
Initial value XXXXXXXX
bit2 bit1 bit0
D2 D1 D0
W W W W
Initial value XXXXXXXX
B
B