Figure 3.8.5C Ready Signal Generation Timing - Fujitsu F2MC-8L MB89620 Series Hardware Manual

Connecting the chip select signal ("L" level output) to the shift inputs of the shift register (H to B)
generates a ready signal (a wait) for 1 to 7 clock cycles. This circuit example connects the chip
select signal to F, G, and H to generate a three-cycle wait. Similarly, connecting to H only
generates a one-cycle wait and connecting to G and H generates a two-cycle wait.
Address decoder
l
The address decoder decodes the address of the external area containing the low-speed
external memory or similar device and generates a "L" level chip select signal when the area is
accessed.
Shift register
l
The chip select signal ("L" level) is connected to the shift inputs (H to A) of the shift register,
starting with the H input. The inputs are loaded on the falling edge of the address latch enable
signal (ALE).
When the ALE signal goes to the "L" level, the shift register shifts in sync with the CLK signal in
the order H, G, F, etc. This successively outputs a series of "L" levels from Q
number of "L" levels output is the number of "L" levels loaded from the shift inputs.
By connecting this output signal to the RDY pin, the CPU extends the bus cycle while the "L"
level is present.
l Address latch
The data input (D) must be output unchanged from the latch output (Q) when the ALE signal
goes to the "H" level. This captures the lower address on the falling edge of the ALE signal.
l Ready signal generation timing
Figure 3.8.5c shows the ready signal generation timing.
CLK
ALE
A08
to A15
AD0
to AD7
CS
QH
(RDY)
MB89620 series
Lower
address
H
Load the "L" level of CS to F, G, and H
(ready operation start).

Figure 3.8.5c Ready Signal Generation Timing

Upper address
Data
G F
, where the
H
H
CS is at the "H" level (access
to memory or other area that
does not require the ready
operation).
CHAPTER 3 CPU
85