Sleep Mode - Fujitsu MB90335 Series Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
6.5.1

Sleep Mode

Sleep mode is mode for stopping the CPU operation clock and the operation other than
CPU continues. When you instruct the transition to the sleep mode with the low-power
consumption mode control register (LPMCR), the transition to the PLL sleep mode is
made if the PLL clock mode is set, the transition to the main sleep mode is made if the
main clock mode is set.
■ Transition to Sleep Mode
If you write "1" to the sleep mode bit (SLP), "1" to the time-base timer mode bit (TMD), and "0" to the stop
mode bit (STP) of the low-power consumption mode control register (LPMCR), the transition to the sleep
mode is made. In this case, the transition to the PLL sleep mode is made if the clock selection register
(CKSCR) is in the state of PLL clock selection bit (MCS)=0, transition to the main sleep mode is made if
MCS=1.
Note:
If you write "1" to the SLP bit and the STP bit of the LPMCR register at the same time, the STP bit is
prioritized and the transition to the stop mode is made.
If you write "1" to the SLP bit and "0" to the TMD bit in the low-power consumption mode control
register, the TMD bit is prioritized and the transition to the time-base timer mode is made.
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Data retention function
In the sleep mode, the contents of the dedicated registers such as accumulators and the internal RAM are
held unchanged.
●
Operation during an interrupt request
Writing "1" to the SLP bit in the LPMCR register does not make the transition to the sleep mode if there is
an interrupt request. Therefore, the CPU executes the next instruction when it is in a state accepting no
interrupts and branches immediately to the interrupt processing routine when it is in a state accepting
interrupts.
●
Pin state
In the sleep mode, the preceding state is retained except for the pins used as the bus input/output or the bus
control.
146 FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
CM44-10137-6E