Intel Agilex User Manual
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Intel Agilex User Manual

Intel Agilex User Manual

Clocking and pll
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UG-20216 | 2019.04.02
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  • Page 1 ® ™ Intel Agilex Clocking and PLL User Guide Subscribe UG-20216 | 2019.04.02 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    3. Intel Agilex Clocking and PLL Design Considerations............ 26 3.1. Guideline: Clock Switchover.................. 26 3.2. Guideline: Timing Closure..................27 3.3. Guideline: Resetting the PLL..................27 3.4. Guideline: Configuration Constraints...............28 4. Document Revision History for the Intel Agilex Clocking and PLL User Guide....29 ® ™ Intel Agilex...

  • Page 3: Intel ® Agilex ™ Clocking And Pll Overview

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 4: Intel Agilex Clocking And Pll Architecture And Features

    This figure shows an example of the clock sectors in an Intel Agilex device, which is implemented as an array of sectors—5 rows and 6 columns in this example. I/O banks are at the top and bottom of the Intel Agilex device.
  • Page 5 The Intel Quartus Prime software creates efficiently balanced clock tress of various sizes, ranging from a single clock sector to the entire device, as shown in the following figure.

  • Page 6: Clock Resources

    Intel Agilex Device Family Pin Connection Guidelines 2.1.3. Clock Control Features The following figure shows the high level description of the Intel Agilex clock control features—clock gating and clock divider. The clock from the I/O PLL output can be gated dynamically. These clock signals along with other clock sources go to the periphery distributed clock multiplexer (DCM).
  • Page 7 Prime software automatically duplicates the SCLK gate to create a clock gate in every sector to which the clock signal is routed. The SCLK gate is suitable for cycle-specific clock gating for high-frequency clocks. The timing of the enable path to the SCLK gate is analyzed by the Intel Quartus Prime software. ®...
  • Page 8 Provides a diagram that shows the resources within a SCLK. 2.1.3.1.3. I/O PLL Clock Gate You can dynamically gate each output counter of the Intel Agilex I/O PLL. This I/O PLL clock gate provides a useful alternative to the root clock gate. The root clock gate can gate only 1 of 7 output counters.

  • Page 9: Plls Architecture And Features

    The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Intel Agilex device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.

  • Page 10: Pll Usage

    2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 Feature I/O Bank I/O PLL Fabric-Feeding I/O Programmable duty cycle Power down mode Bandwidth setting Low, medium, and Medium and high high 2.2.2. PLL Usage I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use the I/O PLLs to: •...

  • Page 11: Pll Architecture

    2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 2.2.4. PLL Architecture Figure 8. I/O Bank I/O PLL High-Level Block Diagram for Intel Agilex Devices To DPA Block For single-ended clock inputs, only the CLKp and CLKn pins have dedicated connection to the PLL.

  • Page 12: Pll Feedback Modes

    2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 You must assert the reset signal every time the I/O PLL loses lock to guarantee the correct phase relationship between the I/O PLL input and output clocks. You can set up the I/O PLL to automatically reset (self-reset) after a loss-of-lock condition using the Intel Quartus Prime parameter editor.
  • Page 13 UG-20216 | 2019.04.02 Normal and source synchronous compensation modes compensate for the insertion delay of a routed core clock. For Intel Agilex devices, you can achieve core clock compensation by routing a dedicated feedback clock from the counter in the I/O PLL to emulate the insertion delay of the compensated counter output clock network.
  • Page 14 Data pin to the IOE register input • Clock input pin to the PLL PFD input The Intel Agilex PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode. ®...
  • Page 15 The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. The Intel Quartus Prime Timing Analyzer reports any phase difference between the two. In normal compensation mode, the delay introduced by the clock network is fully compensated.
  • Page 16 2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 Figure 14. Example of Phase Relationship Between the PLL Clocks in ZDB Mode Phase Aligned PLL Reference Clock at the Input Pin The internal PLL clock PLL Clock at the...

  • Page 17: Clock Multiplication And Division

    Dedicated PLL Clock Outputs fbin Clock Input Pin 2.2.7. Clock Multiplication and Division An Intel Agilex PLL output frequency is related to its input reference clock source by the scale factor: × ) for I/O PLL. The input clock is divided by a pre-scale factor, , and is then multiplied by the feedback factor.

  • Page 18: Programmable Phase Shift

    2.2.10. PLL Cascading Intel Agilex devices support PLL-to-PLL cascading. You can cascade a maximum of two PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL. If you cascade PLLs in your design, the source (upstream) PLL must have a low- bandwidth setting, and the destination (downstream) PLL must have a high-bandwidth setting for I/O PLL.

  • Page 19: Pll Input Clock Switchover

    2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 Intel Agilex devices support the following PLL-to-PLL cascading modes for I/O bank I/O PLL: • I/O-PLL-to-I/O-PLL cascading via dedicated cascade path—upstream I/O PLL and downstream I/O PLL must be in the same I/O column.
  • Page 20 2.2.11.1. Automatic Switchover Intel Agilex I/O PLLs support a fully configurable clock switchover capability. Figure 18. Automatic Clock Switchover Circuit Block Diagram This figure shows a block diagram of the automatic switchover circuit built into the I/O PLL.
  • Page 21 2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 signal indicates which of the two clock inputs ( activeclock inclk0 inclk1 is being selected as the reference clock to the I/O PLL. When the frequency difference between the two clock inputs is more than 20%, the...
  • Page 22 You must choose the backup clock frequency and set the , and counters so that the VCO operates within the recommended operating frequency range. The Intel Quartus Prime software notifies you if a given combination of inclk0 inclk1 frequencies cannot meet this requirement.
  • Page 23 2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 Figure 20. Clock Switchover Using the (Manual) Control extswitch This figure shows a clock switchover waveform controlled by the signal. In this case, both clock extswitch sources are functional and is selected as the reference clock.

  • Page 24: Pll Reconfiguration And Dynamic Phase Shift

    You can delay the clock switchover action by specifying the switchover delay in the Intel FPGA IP cores for the I/O PLL. When you specify the switchover delay, the signal must be held low for at least three cycles for the...
  • Page 25 2. Intel Agilex Clocking and PLL Architecture and Features UG-20216 | 2019.04.02 2.2.13.2. User Calibration The I/O PLL must be recalibrated for any of the following conditions after device power • Dynamic I/O PLL reconfiguration that changes the counter settings is performed.

  • Page 26: Intel Agilex Clocking And Pll Design Considerations

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 27: Guideline: Timing Closure

    I/O PLL. Dynamic phase shift only affects the output clock phase. • The Timing Analyzer in the Intel Quartus Prime software performs timing analysis for the initial PLL settings only. You must verify that your design closes timing after dynamic reconfiguration or dynamic phase shift.

  • Page 28: Guideline: Configuration Constraints

    3. Intel Agilex Clocking and PLL Design Considerations UG-20216 | 2019.04.02 3.4. Guideline: Configuration Constraints The I/O PLL configuration must obey the following constraints: • The phase frequency detector (PFD) and VCO each have a legal frequency range of operation.

  • Page 29: Document Revision History For The Intel Agilex Clocking And Pll User Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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