Related Manuals for Intel Agilex F Series
Summary of Contents for Intel Agilex F Series
- Page 1 ® ™ Intel Agilex F-Series FPGA Development Kit User Guide 683024 Online Version Send Feedback Version: 2022.09.30 UG-20258...
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Page 2: Table Of Contents
A. Development Kit Components..................29 A.1. Intel Agilex FPGA....................29 A.2. Configuration Support..................29 A.2.1. JTAG Chain and Header................29 A.2.2. On-board Intel FPGA Download Cable II .............30 A.3. Clocks........................ 31 A.4. Memory Interfaces....................32 A.5. Transceiver Interfaces..................32 A.6. HPS Interface......................32 A.7. - Page 3 A.8.2. Power Measurement................. 39 A.8.3. Temperature Monitor................39 B. Additional Information....................41 B.1. Safety and Regulatory Information.................41 B.1.1. Safety Warnings..................42 B.1.2. Safety Cautions..................43 B.2. Compliance Information..................46 ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
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Page 4: Overview
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 5: Block Diagram
Conn +12V from PCIe Gold Fingers Feature Summary • Intel Agilex F-Series FPGA, 1400 KLE, 2486- (R24A and R24B) packages • 2x Standard QSFPDD supports both optical and electrical cable interfaces connected to E-Tile transceivers • PCIe x16 Gen 4 golden finger connected to P-Tile transceivers, supports x1/x4/x8/x16 modes •... -
Page 6: Box Contents
1. Overview 683024 | 2022.09.30 1.2. Box Contents Intel Agilex F-Series FPGA Development board, DDR4 DIMM module, USB2.0 Micro cable, Ethernet cable, 240W power adapter and NA/EU/JP/UK cords, ATX power convert cable - 24pin to 6pin. Note: Only one DIMM module is provided with each development kit. -
Page 7: Getting Started
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 8: Design Examples
Contains the instructions on how to program the power power_max10 monitoring function in the Intel MAX 10 board controller (refer to Control on-board power regulator through Power on page 12). Contains the instructions on how to program UBII Intel MAX ubii_max10 ® ™ Intel Agilex... -
Page 9: Power Up The Development Kit
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 10: Control On-Board Clock Through Clock Controller Gui
<package dir>\examples\board_test_system directory. The Clock Controller communicates with the System Intel MAX 10 device through either USB port J13 or 10 pin JTAG header J14. Then System Intel MAX 10 controls these programmable clock parts through a 2-wire I C bus. - Page 11 Sets the programmable oscillator frequency for the selected clock to the value in the output controls for the Si5338. Frequency changes might take several CLKx milliseconds to take effect. You might see glitches on the clock during this time. Intel recommends resetting the FPGA logic after changing frequencies. Import Si5341 has a two-time writable non-volatile memory (NVM).
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Page 12: Control On-Board Power Regulator Through Power Gui
It also collects temperature from FPGA die, power modules and diodes assembled on PCB. Power GUI communicates with System Intel MAX 10 through either USB port J13 or J14. System Intel MAX 10 monitors and controls power regulator, temperature/ voltage/current sensing chips through a 2-wire serial bus. -
Page 13: Board Test System
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 14: The Sys Info Tab
3. When configuration finishes, the design begins running in the FPGA. The corresponding Graphical User Interface (GUI) application tabs that interface with the design are now enabled. If you use the Intel Quartus Prime Programmer for configuration, rather than the BTS GUI, you may need to restart the GUI. -
Page 15: The Gpio Tab
System Intel MAX 10 (VTAP) is always on the JTAG chain, but change the settings of SW4 to low or high to bypass or enable power Intel MAX 10, HPS and Intel Agilex FPGA. System Intel MAX 10 and FPGA should all be in the JTAG chain when configured and running the BTS GUI. -
Page 16: The Qsfpdd Tab
Figure 7. The QSFPDD Tab The following sections describe controls in the QSFPDD tab. Status The Status control displays the following status information during the loopback test: ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... - Page 17 — Pre-tap 3: Specifies the amount of pre-emphasis on the third pre-tap of the transmitter buffer. — Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the transmitter buffer. • Equalizer: Specifies the RX tuning mode for receiver equalizer. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
- Page 18 Insert: Insert a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis. • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
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Page 19: The Ddr4-0 Tab
Data Rate: Displays the XCVR type and data rate of each channel. Figure 9. XCVR- Data Rate 4.1.5. The DDR4-0 Tab This tab allows you to read and write DDR4-0 memory on your board. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... - Page 20 Data Bus: 72 bits (8 bits ECC) wide, reference clock is 100 MHz and the frequency is 1066 MHz double data rate 2133 MT/s. Error Control This control displays data errors detected during analysis and allows you to insert errors: ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
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Page 21: The Ddr4-2 Tab
This tab allows you to read and write DDR4-2 memory on your board. Figure 11. The DDR4-2 Tab The following sections describe the controls on this tab. Start Initiates DDR4 memory transaction performance analysis. Stop Terminates transaction performance analysis. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... -
Page 22: The Ddr4-3 Tab
Determines the number of addresses to use in each iteration of reads and writes. 4.1.7. The DDR4-3 Tab This tab allows you to read and write DDR4-3 memory on your board. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... - Page 23 Data Bus: 72 bits (8 bits ECC) wide, reference clock is 100 MHz and the frequency is 1066 MHz double data rate 2133 MT/s. Error Control This control displays data errors detected during analysis and allows you to insert errors: ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
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Page 24: Bts Test Areas
25 Gbps for NRZ build, but you can manually try it out PAM4 @50 Gbps with hard PRBS pattern with temporary PAM4 build in installer package. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... -
Page 25: Development Kits Hardware And Configuration
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 26: Configure The Fpga Device By As Modes (Default Mode)
683024 | 2022.09.30 5.2. Configure the FPGA device by AS modes (Default Mode) Default SW1 setting and system Intel MAX 10 image support AS configuration mode. Power on and observe FPGA D13 Configuration LED behavior. The Intel Agilex F-Series FPGA Development Kit also supports some HPS interfaces. -
Page 27: Custom Projects For The Development Kit
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 28: Revision History
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 29: Development Kit Components
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 30: On-Board Intel Fpga Download Cable Ii
CPLD devices using the external Intel FPGA Download Cable II dongle. The dongle can be used to program both the Intel Agilex FPGA and Intel MAX 10 CPLD via the external 2x5pin 0.1” programming header. This header uses a shrouded right angle connector and is designed to be accessible from the PCIe bracket side. -
Page 31: Clocks
9DML0441AKILF. Another input of the clock buffer is from PCIe Golden Finger as a system clock of PCIe Gen4. Si510 provides a 50 MHz clock to System Intel MAX 10 and Power Intel MAX 10. Figure 15. -
Page 32: Memory Interfaces
A. Development Kit Components 683024 | 2022.09.30 A.4. Memory Interfaces The Intel Agilex F-Series FPGA Development Kit has four channels of 288 pin DDR4 DIMM 72-bit interfaces: DDR4 DIMM CH0, DDR4 DIMM CH1,DDR4 DIMM CH2 and DDR4 DIMM CH3. DDR4 DIMM CH1 is designed for HPS dedicated applications. The other three memory channels are for FPGA general usage and support both DDR4 and DDR-T (Intel ™... -
Page 33: General Input And Output
OFF= connect power module of VCC_core to main I2C chain. SW3.4 FPGAPMBUS Enable ON = Isolate power module of VCC_core from SDMPMBUS. OFF= connect power module of VCC_core to SDM PMBUS. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... - Page 34 Default Settings SW4.1 JTAG Input Source ON = select PCIe edge as JTAG master when external JTAG is absent. OFF = select On-Board Intel FPGA Download Cable as JTAG master when external JTAG is absent. SW4.2 Power Max10 Bypass ON = bypass Power Max10 in the JTAG chain.
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Page 35: Buttons
QSFPDD1_LED2 A.8. Power The power to the Intel Agilex F-Series FPGA Development Kit is provided from the PCIe slot (up to 75 W) and a secondary Auxiliary 2x4 PCIe power connector capable of an additional 150 W. The development kit does not power up until both the +12 V rails from the PCIe slot and the secondary auxiliary PCIe power connector are detected. - Page 36 A. Development Kit Components 683024 | 2022.09.30 A Intel MAX 10 power sequencer is used to manage the Power-Up sequencing needed to meet the Intel Agilex FPGA Power Sequencing requirements. No Power-down sequencing is required on the Intel Agilex FPGA.
- Page 37 3.0A QSFPDD0_VCC/QSFPDD0_VCCT/QSFPDD0_VCCR Ctlr U63 Max 10W Class 5 Power-up Sequence: (No power down sequence requirement) Board Power On 12V/5V/1p8V_STBY/3p3V_STBY/1p2V_PRE Power Sequence Start Group 1 Group 2 Group 3 ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
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Page 38: Power Sequence
0 12V/5V/1p8V_STBY/3p3V_STBY/1p2V_PRE Power Sequence Start 1 Group1 2 Group2 3 Group3 A.8.1. Power Sequence The Power Sequencing function is implemented by using an Intel MAX 10 device that monitors the "Power_Good" signals of power modules. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide... -
Page 39: Power Measurement
OVERTEMPn ALERTn also routed to the Power Intel MAX 10 CPLD to allow it to immediately sense a temperature fault condition if the board gets too hot. An over temperature warning LED (Red-colored) is connected to the Intel MAX 10 device so software can indicate a visual over temperature warning. - Page 40 C395 10Dpf DXP6 R729 10.0K DXN6 STBY DXP7 C396 DXN7 0.1uF 38, 39, 40, 44, 46, 50 MAIN_I2C_SCL SMBCLK SMBDATA 38, 39, 40, 44, 46, 50 MAIN_I2C_SDA MAX6581 ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
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Page 41: Additional Information
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. -
Page 42: Safety Warnings
To avoid shock, you must ensure that the power cord is connected to a properly wired and grounded receptacle. Ensure that any equipment to which this product is attached to is also connected to properly wired and grounded receptacles. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... -
Page 43: Safety Cautions
Certain components such as heat sinks, power regulators, and processors may be hot. Heatsink fans are not guarded. Power supply fan may be accessible through guard. Care should be taken to avoid contact with these components. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback... - Page 44 Public Switched Telecommunication Network (PSTN) as it might result in disruption of the network. No formal telecommunication certification to FCC, R&TTE Directive, or other national requirements have been obtained. ® ™ Intel Agilex F-Series FPGA Development Kit User Guide Send Feedback...
- Page 45 Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.
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Page 46: Compliance Information
B. Additional Information 683024 | 2022.09.30 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste. B.2. Compliance Information...