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Intel Altera Agilex 7 F Series User Manual
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Intel Altera Agilex 7 F Series User Manual

Intel Altera Agilex 7 F Series User Manual

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Agilex
Tiles) Development Kit User Guide
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7 FPGA F-Series (2 × F-
739942
2024.12.20

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Summary of Contents for Intel Altera Agilex 7 F Series

  • Page 1 Explore more resources ® Altera Design Hub ™ Agilex 7 FPGA F-Series (2 × F- Tiles) Development Kit User Guide 739942 Online Version Send Feedback 2024.12.20...

  • Page 2: Table Of Contents

    Prime Software and Driver Installation............9 2.3.1. Installing the Quartus Prime Pro Edition Software......... 10 2.3.2. Installing the Development Kit..............11 2.3.3. Installing the Intel FPGA Download Cable II Driver........11 3. Development Kit Setup....................13 3.1. Default Settings....................13 3.2. Powering Up the Development Board..............14 4.
  • Page 3 A.2. FPGA Configuration....................47 A.2.1. Programming the FPGA over On-Board Intel FPGA Download Cable II..... 48 A.2.2. Programming the FPGA over an External Intel FPGA Download Cable II... 48 A.3. Default Switch and Jumper Settings............... 49 A.3.1. Switch Description................... 49 A.3.2.

  • Page 4: Overview

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Block Diagram

    1. Overview 739942 | 2024.12.20 1.1. Block Diagram Figure 2. Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit Block Diagram (DK- DEV-AGF023FA) DDR4 x72 DIMM / DDR-T (1 rank up to 3,200 Mbps) QSPI uUSB Flash QSPI JTAG Flash MAX®...

  • Page 6: Feature Summary

    — 2 Gb flash for AS x4 — Dual 2 Gb flash for Avalon streaming interface x16 — JTAG header for device programming — Built-in Intel FPGA Download Cable II for device programming • Programmable clock sources •...

  • Page 7: Box Contents

    1. Overview 739942 | 2024.12.20 • Buttons, switches, and LEDs — CPU reset push button — PCIe reset push button — CXL reset push button — HPS reset push button — Four dedicated user LEDs — Board power good LED —...

  • Page 8: Recommended Operating Conditions

    1. Overview 739942 | 2024.12.20 1.4. Recommended Operating Conditions Table 2. Recommended Operating Conditions Operating Condition Range of Values Ambient operating temperature range 0°C to 35°C Maximum ICC load current 150 A Maximum ICC load transient percentage FPGA maximum power supported by active heatsink/fan 150 W Related Information Handling the Board...

  • Page 9: Getting Started

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 10: Installing The Quartus Prime Pro Edition Software

    2. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus Prime Pro Edition software installation directory. If you have difficulty installing the Quartus Prime software, refer to the Intel FPGA Software Installation and Licensing. Related Information •...

  • Page 11: Installing The Development Kit

    2.3.3. Installing the Intel FPGA Download Cable II Driver The Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit includes onboard Intel FPGA ® Download Cable II circuits for FPGA and system MAX 10 programming.
  • Page 12 2. Getting Started 739942 | 2024.12.20 On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions. Related Information • Cable and Adapter Drivers Information •...

  • Page 13: Development Kit Setup

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 14: Powering Up The Development Board

    3. Development Kit Setup 739942 | 2024.12.20 Switch Default Position Function —SI52204 (U25) PCIe clock power down. SW4[4] • ON powers down the PCIe clocks • OFF powers on the PCIe clocks (Default) —PCIe source selection. SW4[3] refclk • ON selects 100 MHz clock source from the PCIe edge fingers •...
  • Page 15 3. Development Kit Setup 739942 | 2024.12.20 Note: Use only the supplied power supply. Power regulation circuits on the board can be damaged by power supplies with greater voltage. 3. Set the power switch ( ) to the ON position. When the board powers up, the blue power-on LED ( ) illuminates signaling the board is ready for use.

  • Page 16: Board Test System

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 17: Set Up Bts Gui Running Environment

    4. Board Test System 739942 | 2024.12.20 4.1. Set Up BTS GUI Running Environment To run BTS GUI, including Power Monitor and Clock Controller GUIs, you need to download and install Java runtime including OpenJDK and OpenJFX on your systems and set up the running environment.

  • Page 18: Setting Up The Quartus Prime Software For Bts Operation

    4. Board Test System 739942 | 2024.12.20 You have the following two directories on your Linux system: — /opt/Java/jre — /opt/Java/jfx 4.1.4. Setting Up the Quartus Prime Software for BTS Operation You must install the Quartus Prime software to support the silicon on the development kit.
  • Page 19 4. Board Test System 739942 | 2024.12.20 Figure 6. BTS Folder You can run BTS GUI easily with the following scripts. 1. On Windows system, double click the files to run the BTS, Clock .bat Controller, or Power Monitor GUI. Figure 7.

  • Page 20: Test The Functionality Of The Development Kit

    4. Board Test System 739942 | 2024.12.20 Figure 8. Linux Console Note: or shell script checks the Java environment settings, copy necessary files, .bat and give some prompts if the environment is not set up correctly. The GUI displays the application tab corresponding to the design running in the FPGA. If the design loaded in the FPGA is not supported by the BTS GUI, you receive a message prompting you to configure your board with a valid BTS design.
  • Page 21 4. Board Test System 739942 | 2024.12.20 Figure 9. The Configure Menu (DK-DEV-AGF027F1ES) Figure 10. The Configure Menu (DK-DEV-AGF023FA) ™ Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide Send Feedback...

  • Page 22: The Sys Info Tab

    4. Board Test System 739942 | 2024.12.20 To configure the FPGA with a test system design, follow these steps: 1. On the Configure menu, click the Configure command that corresponds to the functionality you want to test. 2. In the dialog box that appears, click Configure to download the corresponding design's SRAM Object File ( ) to the FPGA.

  • Page 23: The Gpio Tab

    4. Board Test System 739942 | 2024.12.20 Figure 12. The Sys Info Tab (DK-DEV-AGF023FA) The following sections describe the controls on the Sys Info tab. Board Information The board information control displays static information about your board. • Board Name: Indicates the official name of the board given by the BTS. •...
  • Page 24 4. Board Test System 739942 | 2024.12.20 Figure 13. The GPIO Tab (DK-DEV-AGF027F1ES) ™ Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide Send Feedback...

  • Page 25: The Xcvr Tab

    4. Board Test System 739942 | 2024.12.20 Figure 14. The GPIO Tab (DK-DEV-AGF023FA) The following sections describe the controls on the GPIO tab. User LEDs The User LEDs control displays the current state of the user LEDs. Toggle the LED buttons to turn the board LEDs on and off.
  • Page 26 4. Board Test System 739942 | 2024.12.20 4.2.5.1. The QSFP NRZ Tab Figure 15. The QSFP NRZ Tab The following sections describe controls in the QSFP NRZ tab. Status The Status control displays the following status information during the loopback test: •...

  • Page 27: Pma Setting

    4. Board Test System 739942 | 2024.12.20 PMA Setting The PMA Setting control allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis: • Serial Loopback: Displays the signal status between the transmitter and the receiver.

  • Page 28: Error Control

    4. Board Test System 739942 | 2024.12.20 Error Control This control displays data errors detected during analysis and allows you to insert errors: • Detected Errors: Displays the number of data errors detected in the received bit stream. • Inserted Errors: Displays the number of errors inserted into the transmit data stream.
  • Page 29 4. Board Test System 739942 | 2024.12.20 Figure 18. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab Similar control functions with the QSFP NRZ tab. ™ Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide Send Feedback...
  • Page 30 4. Board Test System 739942 | 2024.12.20 Figure 19. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab Similar control functions with the QSFP NRZ tab. ™ Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide Send Feedback...

  • Page 31: The Memory Tab

    4. Board Test System 739942 | 2024.12.20 Figure 20. The QSFPDD PAM4 Tab 4.2.6. The Memory Tab This tab allows you to read and write DDR4 DIMM on your board. DDR4 DIMM1 and DDR4 DIMM2 can be tested on DK-DEV-AGF027F1ES while there is only one DDR4 DIMM on DK-DEV-AGF023FA.

  • Page 32: Performance Indicators

    4. Board Test System 739942 | 2024.12.20 Figure 21. The RDIMM1 Tab The following sections describe controls on this tab. Start Initiates DDR4 memory transaction performance analysis. Stop Terminates transaction performance analysis. Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: •...

  • Page 33: Test Control

    4. Board Test System 739942 | 2024.12.20 Test Control • Test Size: You can choose the size of the memory to test. The available options are 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, 8 GB, and 16 GB (default).

  • Page 34: Control On-Board Clock Through Clock Controller Gui

    4. Board Test System 739942 | 2024.12.20 4.3. Control On-Board Clock through Clock Controller GUI The Clock Controller GUI can change the on-board programmable PLLs to a large range of customized frequency. The instructions to run Clock Controller GUI are stated in the Running the BTS GUI section.

  • Page 35: Related Information

    4. Board Test System 739942 | 2024.12.20 Import ZL30733 has a multiple time writable non-volatile memory (NVM). You can generate the register list with the following format: • Register Write Command Line: X ,<register_address> , <data_bytes>— <register_address> and <data_bytes>, whose prefix must be “0x” are in hexadecimal •...

  • Page 36: Data Record

    4. Board Test System 739942 | 2024.12.20 Figure 24. Power Monitor GUI The following sections describe the details of the Power Monitor GUI. Display Configure • Speed Adjustment: Adjusts the update rate of the current curve • Reset: Regenerates the graph Data Record When the box is checked, the telemetry data of the selected power rail can be recorded.
  • Page 37 4. Board Test System 739942 | 2024.12.20 QSFPDD Plug QSFPDD loopback module in before you configure QSFPDD NRZ/PAM4 example build through the BTS GUI. DDR4 DIMM Plug the DDR4 DIMM module which is shipped alone with DK-DEV-AGF027F1ES in and DK-DEV-AGF023FA in The BTS GUI only supports fabric memory interfaces, namely DDR4 DIMM1 and DDR4 DIMM2 in DK-DEV-AGF027F1ES and DDR4 DIMM in DK-DEV-AGF023FA.

  • Page 38: Development Kit Hardware And Configuration

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 39 5. Development Kit Hardware and Configuration 739942 | 2024.12.20 Table 6. Image Download Selection Image Selection J106 J105 Notes Image 0 Installed Installed Image 0—Default Image 1 Installed Open Image 1 Image 2 Open Installed Image 2 Image 3 Open Open Image 3 ™...

  • Page 40: Custom Projects For The Development Kit

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 41: Document Revision History For The Agilex 7 Fpga F-Series (2 × F-Tiles) Development Kit User Guide

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 42 • Updated development kit name to "Intel Agilex 7 FPGA F-Series Development Kit." • Retitled the document from Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide to ® Intel Agilex 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide.

  • Page 43: Development Kit Components

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 44 PCIe control DIP switch Enables PCIe link widths x1, x4, x8, and x16. Intel FPGA Download Cable II Selects between the on-board Intel FPGA Download Cable II or selection switch external Intel FPGA Download Cable II connected to the header.

  • Page 45: Status Elements

    A. Development Kit Components 739942 | 2024.12.20 Board Type Description Reference CXL_PCIe_PERSTN push-button Sends an active low signal to the CXL connector PERSTN pin. Configuration image selection Use together with to select image stored in for Avalon J105 J106 streaming interface x16. Configuration image selection Use together with to select image stored in...
  • Page 46 Table 13. Communication Ports Board Reference Type Description 10-pin JTAG header For connecting an external Intel FPGA Download Cable II dongle. Micro-USB connector For connecting to the on-board Intel FPGA Download Cable II. Table 14. Miscellaneous Ports Board Reference Type...

  • Page 47: Max 10 Cpld System Controller

    The development board utilizes the 10M50 system controller, an MAX 10 CPLD for the following purposes: • Power sequencing control • FPGA configuration from flash memory • On-board Intel FPGA Download Cable II • Power monitoring • Temperature monitoring • Fan control •...

  • Page 48: Programming The Fpga Over On-Board Intel Fpga Download Cable Ii

    A. Development Kit Components 739942 | 2024.12.20 Ensure the following: • The Quartus Prime Programmer and the Intel FPGA Download Cable II driver are installed on the host computer. • The Micro-USB cable is connected to the FPGA development board.

  • Page 49: Default Switch And Jumper Settings

    A. Development Kit Components 739942 | 2024.12.20 Figure 27. Programming the FPGA over an External Intel FPGA Download Cable II Block Diagram External JTAG Header (J3) External JTAG FPGA JTAG Agilex™ 7 MAX® 10 FPGA (U8) Intel® FPGA Download Cable II...
  • Page 50 A. Development Kit Components 739942 | 2024.12.20 Table 17. SW2—Single DIP for Intel FPGA Download Cable II Selection Switch Position Board Label Function Default Position USB MAX JTAG SEL ON for on-board Intel FPGA Download Cable II OFF for external Intel FPGA Download Cable II Table 18.

  • Page 51: Jumper Description

    A. Development Kit Components 739942 | 2024.12.20 Table 23. S[1–4, 6]—Various Push-Button RESET Switches Switch Function Used to send RESET to CPU Used to send RESET to HPS Used to send PERSTN to PCIe Used to send 2nd PERSTN to PCIe Used to send PERSTN to CXL PCIe A.3.2.

  • Page 52: Leds

    A. Development Kit Components 739942 | 2024.12.20 Table 26. Switches Board Reference Schematic Signal Name I/O Standard SW1.1 PCIE_EP_PRSNT_Nx16 3.3V SW1.2 PCIE_EP_PRSNT_Nx8 3.3V SW1.3 PCIE_EP_PRSNT_Nx4 3.3V SW1.4 PCIE_EP_PRSNT_Nx1 3.3V USB_MAX_JTAG_SEL 3.3V SW3.1 FPGA_1V8_MSEL1 1.8V SW3.2 FPGA_1V8_MSEL2 1.8V SW3.3 BMC_JTAG_EN 1.8V SW3.4 HPS_JTAG_BYPASS 1.8V...

  • Page 53: Components And Interfaces

    The PCI Express interface supports auto-negotiating channel width from x1 to x4 to x8 to x16 by using PCIe Intel FPGA IP. You can also configure this board to a x1, x4, x8, or x16 interface through a DIP switch that connects the...
  • Page 54 A. Development Kit Components 739942 | 2024.12.20 Edge Finger Schematic Signal FPGA Pin Number I/O Standard Description Pin Number Name FRUID EEPROM 1.8V SMB data PCIE_3V3_EP_SMBDAT (U2) — — Link with DIP switch PCIE_EP_PRSNT_N (SW1) — — Link with DIP switch PCIE_EP_PRSNT_Nx1 (SW1) —...
  • Page 55 A. Development Kit Components 739942 | 2024.12.20 Edge Finger Schematic Signal FPGA Pin Number I/O Standard Description Pin Number Name 1.4 V PCML Receive bus PCIE_EP_TX_P7 1.4 V PCML Receive bus PCIE_EP_TX_P8 1.4 V PCML Receive bus PCIE_EP_TX_P9 1.4 V PCML Receive bus PCIE_EP_TX_P10 1.4 V PCML...

  • Page 56: Qsfp-Dd Interface

    A. Development Kit Components 739942 | 2024.12.20 Edge Finger Schematic Signal FPGA Pin Number I/O Standard Description Pin Number Name 1.4 V PCML Transmit bus PCIE_EP_RX_P9 1.4 V PCML Transmit bus PCIE_EP_RX_P10 1.4 V PCML Transmit bus PCIE_EP_RX_p11 1.4 V PCML Transmit bus PCIE_EP_RX_P12 1.4 V PCML...

  • Page 57: Related Information

    A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description AR55 True Differential Signaling QSFPDD Receive Channel 0 Positive QSFPDD_RX0_P AT54 True Differential Signaling QSFPDD Receive Channel 0 negative QSFPDD_RX0_N True Differential Signaling QSFPDD Receive Channel 1 Positive QSFPDD_RX1_P True Differential Signaling QSFPDD Receive Channel 1 negative...

  • Page 58: Cxl Interface

    The Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit board provides a CXL connector interface for cabling to an Intel-designed M.2 SSD daughter card supporting M-Keying. This interface connects to four 28 Gbps F-Tile lanes of the Agilex 7 FPGA.

  • Page 59: Ddr4 Dimm1 Interface

    A. Development Kit Components 739942 | 2024.12.20 Table 31. CXL Pin Assignments Schematic Signal Name FPGA Pin Number I/O Standard Description BW49 True Differential Signaling CXL Transmit Channel 0 Positive CXL_TX_P0 BY48 True Differential Signaling CXL Transmit Channel 0 Negative CXL_TX_N0 BV52 True Differential Signaling...
  • Page 60 A. Development Kit Components 739942 | 2024.12.20 Table 32. DIMM1 Pin Assignments Schematic Signal Name FPGA Pin Number I/O Standard Description DC31 1.2 V HS LVCMOS DDR4 DIMM1 DQ0 data DDR4_DIMM1_DQ0 DD30 1.2 V HS LVCMOS DDR4 DIMM1 DQ1 data DDR4_DIMM1_DQ1 CY30 1.2 V HS LVCMOS...
  • Page 61 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description 1.2 V HS LVCMOS DDR4 DIMM1 DQ20 data DDR4_DIMM1_DQ20 1.2 V HS LVCMOS DDR4 DIMM1 DQ21 data DDR4_DIMM1_DQ21 1.2 V HS LVCMOS DDR4 DIMM1 DQ22 data DDR4_DIMM1_DQ22 1.2 V HS LVCMOS DDR4 DIMM1 DQ23 data...
  • Page 62 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description Positive for byte lane 4 DJ25 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe DDR4_DIMM1_DQS_N4 Negative for byte lane 4 DF24 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for DDR4_DIMM1_DBI_N4 byte lane 4...
  • Page 63 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description DA23 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe DDR4_DIMM1_TDQS_N15 for byte lane 6 CY12 1.2 V HS LVCMOS DDR4 DIMM1 DQ56 data DDR4_DIMM1_DQ56 DC13 1.2 V HS LVCMOS...
  • Page 64 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description CT24 1.2 V HS LVCMOS DDR4 DIMM1 Bank Address 1 DDR4_DIMM1_BA1 CW25 1.2 V HS LVCMOS DDR4 DIMM1 Bank Address 0 DDR4_DIMM1_BA0 CV24 1.2 V HS LVCMOS DDR4 DIMM1 Address 17 DDR4_DIMM1_A17 CR27...

  • Page 65: Ddr4 Dimm2 Interface

    A. Development Kit Components 739942 | 2024.12.20 A.5.6. DDR4 DIMM2 Interface The Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit board provides two DDR4 x72 DIMM interfaces connected to the FPGA fabric. DIMM2 is connected to the Agilex 7 IO96 of banks 2E and 2F.
  • Page 66 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description CY46 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for DDR4_DIMM2_DBI_N1 byte lane 1 DA47 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe DDR4_DIMM2_TDQS_N10 for byte lane 1 CN49...
  • Page 67 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description CW49 1.2 V HS LVCMOS DDR4 DIMM2 DQ34 data DDR4_DIMM2_DQ34 CR49 1.2 V HS LVCMOS DDR4 DIMM2 DQ35 data DDR4_DIMM2_DQ35 CW53 1.2 V HS LVCMOS DDR4 DIMM2 DQ36 data DDR4_DIMM2_DQ36 CV52...
  • Page 68 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description CP36 1.2 V HS LVCMOS DDR4 DIMM2 DQ55 data DDR4_DIMM2_DQ55 CP38 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe DDR4_DIMM2_DQS_P6 Positive for byte lane 6 CN39 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe...
  • Page 69 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description CT38 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for DDR4_DIMM2_DBI_N8 byte lane 8 CR39 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe DDR4_DIMM2_TDQS_N17 for byte lane 8 DJ33...

  • Page 70: Ddr4 Component Interface

    A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description DD40 1.2 V HS LVCMOS DDR4 DIMM2 On Die Termination 0 DDR4_DIMM2_ODT0 DA43 1.2 V HS LVCMOS DDR4 DIMM2 Activate Command DDR4_DIMM2_ACT_N CY42 1.2 V HS LVCMOS DDR4 DIMM2 Chip Select 0 DDR4_DIMM2_CS_N0 DC43...
  • Page 71 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description 1.2 V HS LVCMOS DDR4 component DQS 1 strobe DDR4_COMP_DQS_N1 negative 1.2 V HS LVCMOS DDR4 component Data Bus Inversion DDR4_COMP_DBI_N1 for byte lane 1 1.2 V HS LVCMOS DDR4 component DQ16 data DDR4_COMP_DQ16...
  • Page 72 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description 1.2 V HS LVCMOS DDR4 component DQ39 data DDR4_COMP_DQ39 1.2 V HS LVCMOS DDR4 component DQS 4 strobe DDR4_COMP_DQS_P4 positive 1.2 V HS LVCMOS DDR4 component DQS 4 strobe DDR4_COMP_DQS_N4 negative...

  • Page 73: Hps Io48 Interface

    The Agilex 7 FPGA F-Series (2 × F-Tiles) Development Kit board connects the 48 HPS I/Os ( ) to a mezzanine connector for installing HPS_IOA[24:1] HPS_IOB[24:1] the Intel HPS IO48 daughter card. This daughter card provides the HPS with USB, UART, Ethernet, SD card, I C, and JTAG accessibility. Table 35. HPS Pin Assignments...
  • Page 74 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description AU13 1.8 V LVCMOS Ethernet RX Data 3 HPS_GPIO23 AF10 1.8 V LVCMOS GPIO IO0 HPS_GPIO24 AU11 1.8 V LVCMOS GPIO IO1 HPS_GPIO25 1.8 V LVCMOS UART TX HPS_GPIO26 AT12...

  • Page 75: I 2 C Block Diagram

    A. Development Kit Components 739942 | 2024.12.20 Figure 29. C Block Diagram LTC3888-1 SPI Bus ADDR=55h Intel® FPGA VCC, FX2_SCL/SDA Download Cable VCC HSSI MAX® 10 (U61) System Controller (U49) (U5) ZL30733 MAX_12C_SCL/SDA ADDR=70h Clock (U23) ADDR=42h DIMM1 DIMM2 ADDR=A0h...

  • Page 76: Max 10 Spi Bus

    A. Development Kit Components 739942 | 2024.12.20 A.7. MAX 10 SPI Bus The MAX 10 device uses the SPI bus for reading telemetry information from the Analog Devices LTC3888* VCC core controller. Table 38. SPI Signals Schematic Signal Name FPGA Pin Number I/O Standard Description 1.8 V CMOS...

  • Page 77: Hps Daughter Card

    A. Development Kit Components 739942 | 2024.12.20 Table 39. On-Board Oscillators Sources for the FPGA Source Schematic Signal Frequency I/O Standard Agilex 7 Pin Application Name (MHz) Number (P/N) Differential G43/F44 IEEE 1588 TOD master TOD_MASTER_CLK_ clock 125M_P/N LVDS CK18/CL19 General-purpose FPGA clock CLK_FPGA_100M_P Differential...
  • Page 78 A. Development Kit Components 739942 | 2024.12.20 Figure 31. HPS Daughter Card Table 40. HPS I/O 48 Signals Schematic Signal Name FPGA Pin Number I/O Standard Description AC15 1.8 V LVCMOS USB clock HPS_GPIO0 AL15 1.8 V LVCMOS USB STP HPS_GPIO1 AJ11 1.8 V LVCMOS...
  • Page 79 A. Development Kit Components 739942 | 2024.12.20 Schematic Signal Name FPGA Pin Number I/O Standard Description AP14 1.8 V LVCMOS Ethernet RX Data1 HPS_GPIO19 1.8 V LVCMOS Ethernet TX Data2 HPS_GPIO20 AT14 1.8 V LVCMOS Ethernet TX Data3 HPS_GPIO21 AF12 1.8 V LVCMOS Ethernet RX Data2 HPS_GPIO22...

  • Page 80: System Power

    A. Development Kit Components 739942 | 2024.12.20 A.10. System Power This section describes the Agilex 7 FPGA development board's power supply. A laptop style DC power supply is provided with the development kit. Use only the supplied power supply. The power supply has an auto sensing input voltage of 100–240 V AC power and output of 12 V DC power at 20 A to the development board.

  • Page 81: Power Distribution System

    A. Development Kit Components 739942 | 2024.12.20 This power supply provides the entire power to the board without the need to obtain power from the PCIe slot. The power switch SW5 controls powering the board on or off. Figure 33. As a Standalone Evaluation Board Powered by Included Power Supply A.12.

  • Page 82: Power Measurement

    A. Development Kit Components 739942 | 2024.12.20 A.13. Power Measurement There are eight power supply rails that have on-board voltage, current, and wattage sense capabilities. An I C bus connects seven of these voltage regulator devices to the MAX 10 system controller for power telemetry data reporting. The V rail for the FPGA core power is measured by the MAX 10 using the SPI bus interface between the MAX 10 and VCC core controller.

  • Page 83: Developer Resources

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 84: Safety And Regulatory Compliance Information

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 85: Safety Warnings

    C. Safety and Regulatory Compliance Information 739942 | 2024.12.20 C.1.1. Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system.

  • Page 86: Power Cord Requirements

    C. Safety and Regulatory Compliance Information 739942 | 2024.12.20 Power Cord Requirements The plug on the power cord must be a grounding-type male plug designed for use in your region. It must have certification marks showing certification by an agency in your region.

  • Page 87: Cooling Requirements

    C. Safety and Regulatory Compliance Information 739942 | 2024.12.20 Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan. Electro-Magnetic Interference (EMI) This equipment has not been tested for compliance with emission limits of FCC and similar international regulations.

  • Page 88: Electrostatic Discharge (Esd) Warning

    Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

  • Page 89: Compliance Information

    C. Safety and Regulatory Compliance Information 739942 | 2024.12.20 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste.

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