Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1878

ADSP-SC58x PCIE Register Descriptions
Endpoint Base Address Register 4
The
PCIE_EP_BAR4_[n]
This register also determines the use of the prefetch capability. For more information, see the PCI Express Base
Specification, Rev. 3.0.
ST[11:0] (R/W)
Start
PF (R/W)
Prefetch
ST[27:12] (R/W)
Start
Figure 29-96: PCIE_EP_BAR4_[n] Register Diagram
Table 29-105: PCIE_EP_BAR4_[n] Register Fields
Bit No.
(Access)
31:4 ST
(R/W)
3 PF
(R/W)
2:1 TYPE
(R/W)
0 MIO
(R/W)
29–174
register forms bits [31:x] of the start address of the address region to be translated.
15 14 13 12 11
0 0 0 0
31 30 29 28 27
0 0 0 0
Bit Name
Start.
The PCIE_EP_BAR4_[n].ST bit field forms bits [31:x] of the start address of the
address region to be translated.
Prefetch.
The PCIE_EP_BAR4_[n].PF bit is usually set to one if there are no side effects on
reads. The device returns all bytes on reads regardless of the byte enables, and host
bridges can merge processor writes into this range without causing errors. Bit must be
set to zero otherwise.
Type.
Memory I/O.
The PCIE_EP_BAR4_[n].MIO bit indicates memory space.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10 9 8 7 6 5 4
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
0 Locate anywhere in 32-bit access space
1 Reserved
2 Locate anywhere in 62-bit access space
3 Reserved
0 Memory space
1 I/O space
3 2 1 0
1 0 0 0
MIO (R/W)
Memory I/O
TYPE (R/W)
Type
18 17 16
0 0 0 0