Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1856

ADSP-SC58x PCIE Register Descriptions
DMA Write Error Status Register
The
PCIE_DMAWR_ERRSTAT_[n]
Figure 29-74: PCIE_DMAWR_ERRSTAT_[n] Register Diagram
Table 29-83: PCIE_DMAWR_ERRSTAT_[n] Register Fields
Bit No.
(Access)
23:16 LLSTERR
(R/NW)
7:0 APPERR
(R/NW)
29–152
register reports various write errors.
15 14 13
0 0 0
APPERR (R)
Application Read Error Detected
31 30 29
0 0 0
LLSTERR (R)
Linked List Element Fetch Error Detected
Bit Name
Linked List Element Fetch Error Detected.
The PCIE_DMAWR_ERRSTAT_[n].LLSTERR bit provides notice that the DMA
write channel has received an error response. This response comes from the peripheral
or SCB bus (or the RTRGT1 interface when the peripheral or SCB Bridge is not used)
while reading a linked list element from local memory. Each bit corresponds to a
DMA channel. Bit [0] corresponds to channel 0.
• Enabling: For details, see "Interrupts and Error Handling".
• Masking: The DMA write interrupt Mask register has no effect on this register.
• Clearing: Programs must write a 1'b1 to the corresponding channel bit in the
Abort interrupt field of the "DMA Write Interrupt Clear Register"
(DMA_WR_INT_CLEAR_OFF) to clear this error bit.
Application Read Error Detected.
The PCIE_DMAWR_ERRSTAT_[n].APPERR bit provides notice that the DMA
write channel has received an error response. This response comes from the peripheral
or SCB bus (or the RTRGT1 interface when the peripheral or SCB Bridge is not used)
while reading data from it. Each bit corresponds to a DMA channel. Bit [0] corre-
sponds to channel 0.
• Enabling: For details, see "Interrupts and Error Handling".
• Masking: The DMA write interrupt Mask register has no effect on this register.
• Clearing: Programs must write a 1'b1 to the corresponding channel bit in the
Abort interrupt field of the "DMA Write Interrupt Clear Register"
(DMA_WR_INT_CLEAR_OFF) to clear this error bit.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0