Usart Receiver Tolerance To Clock Deviation; Table 169. Usart Receiver Tolerance When Div Fraction Is 0 - ST STM32F423 Reference Manual

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Table 168. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
15 7.168 MBps
16 7.3728 MBps
18 9 MBps
20 10.5 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
28.4.5

USART receiver tolerance to clock deviation

The USART asynchronous receiver works correctly only if the total clock system deviation is
smaller than the USART receiver tolerance. The causes that contribute to the total deviation
are:
•
DTRA: Deviation due to the transmitter error (also includes the deviation of the
transmitter local oscillator)
•
DQUANT: Error due to the baud rate quantization of the receiver
• DREC: Deviation of the receiver local oscillator
•
DTCL: Deviation due to the transmission line (generally due to the transceivers that
can introduce an asymmetry between the low-to-high transition timing and the
high-to-low transition timing)
DTRA + DQUANT + DREC + DTCL < USART receiver tolerance
The USART receiver tolerance to properly receive data is equal to the maximum tolerated
deviation and depends on the following choices:
•
10- or 11-bit character length defined by the M bit in the USART_CR1 register
•
oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
•
use of fractional baud rate or not
•
use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register
M bit
0
1
906/1324
oversampling by 8
Oversampling by 8 (OVER8=1)
f = 42 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
NA NA
NA NA
NA NA
NA NA

Table 169. USART receiver tolerance when DIV fraction is 0

OVER8 bit = 0
ONEBIT=0
3.75%
3.41%
RM0430 Rev 8
= 42 MHz or f
PCLK
(1)(2)
(continued)
% Error =
(Calculated -
Actual
Desired)B.Rate
/Desired B.Rate
NA 7 MBps
NA 7.636 MBps
NA 9.333 MBps
NA 10.5 MBps
ONEBIT=1 ONEBIT=0
4.375%
3.97%
= 84 MHz,
PCLK
f = 84 MHz
PCLK
Value
programmed
in the baud
rate register
1.5
1.375
1.125
1
OVER8 bit = 1
ONEBIT=1
2.50% 3.75%
2.27% 3.41%
%
Error
2.34
3.57
3.7
0