ARM ETB11 Technical Reference Manual

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ETB11

™

Revision: r0p1

Technical Reference Manual

ARM DDI 0275D

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Summary of Contents for ARM ETB11

Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Address generation ................... 2-10 BIST interface ................... 2-11 TAP controller ................... 2-12 Trace RAM interface ................. 2-15 2.10 Clocks, and resets ..................2-17 2.11 AHB transfers .................... 2-19 ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 4 Contents Chapter 3 Programmer’s Model About the programmer’s model ..............3-2 Register descriptions .................. 3-4 Software access to the ETB11 using the AHB interface ......3-11 Chapter 4 Timing Requirements AHB interface ..................... 4-2 CLK domain ....................4-4 IEEE1149.1 interface .................. 4-6...
Page 5 IEEE1149.1 interface timing requirements ..............4-6 Table A-1 Signal descriptions ....................A-3 Table B-1 ETB11 connection guide ................... B-2 Table B-2 ETB11 to generic trace port interface connections ........... B-3 ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 7 Software write cycle with synchronous CLK and HCLK .......... 2-25 Figure 4-1 AHB interface signals ....................4-2 Figure 4-2 CLK domain signals ....................4-4 Figure 4-3 IEEE1149.1 interface signals ..................4-6 ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 9 Preface ™ This preface introduces the ARM11 Embedded Trace Buffer (ETB11 ) Technical Reference Manual. It contains the following sections: • About this document on page x • Feedback on page xiv. ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 10: Preface
Identifies the minor revision or modification status of the product. Intended audience This document has been written for experienced hardware and software engineers who want to design or obtain trace information from chips that use ARM cores with the ETM facility. Using this manual...
Page 11 Preface Appendix B Integrating the ETB11 This appendix describes how to integrate the ETB11 if you are not using the ETK11 Integration Kit. Conventions This section describes the conventions that this manual uses: • Typographical • Timing diagrams on page xii •...
Page 12: Key To Timing Diagram Conventions
Peripheral Bus APB reset signals. These are named HRESETn and PRESETn respectively. Prefix P Denotes an APB signal. Prefix R Denotes AXI read channel signals. Prefix W Denotes AXI write channel signals. Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 13 ARM periodically provides updates and corrections to its documentation. See for current errata sheets, addenda, and the ARM Frequently Asked http://www.arm.com Questions. ARM publications This document contains information that is specific to the ETB11. Refer to the following documents for other relevant information: ™ • ETB11 Implementation Guide (ARM DII 0067) •...
Page 14: Feedback
Preface Feedback ARM Limited welcomes feedback both on the ETB11 r0p1, and on the documentation. Feedback on the ETB11 If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments.
Page 15 Chapter 1 Introduction This chapter introduces the Embedded Trace Buffer (ETB11) and its features. It contains the following sections: • About the Embedded Trace Buffer on page 1-2 • ETM versions and variants on page 1-5 • Silicon revision on page 1-6.
Page 16: Chapter 1 Introduction
The solution is to provide a buffer area on-chip where the trace information is stored, and read from the chip later, at a slower rate. The ETB11 stores data produced by the ETM11RV. The buffered data can then be accessed by the debugging tools using a JTAG (IEEE 1149.1) interface, as shown in Figure 1-1.
Page 17 This buffered data can also be accessed through an AHB slave-based AHB interface included as part of the ETB11. This enables software running on the processor to read the trace data generated by the ETM11RV.
Page 18 Boundary scan is a methodology enabling complete controllability and observability of the boundary pins of a JTAG-compatible device by software control. This capability enables in-circuit testing without requiring specially designed in-circuit test equipment. Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 19: Etm Versions And Variants
Introduction ETM versions and variants The ETB11 is an enhanced version of the ETB that is designed to support the higher operating speeds of ETM11RV. Although ETB11 supports older ETM protocols, it is intended for use with ETM11RV only. For this reason this document only describes details related to storing trace from ETM11RV.
Page 20: Silicon Revision
Introduction Silicon revision This manual is for ETB11 r0p1. ETB11 r0p1 includes corrections for errata in ETB11 r0p0. Further information can be found in the ETB11 errata list. Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 21 Chapter 2 Functional Description This chapter describes how the ETB11 operates. It contains the following sections: • Functional information on page 2-2 • Operation on page 2-4 • Control logic on page 2-6 • Data Formatter on page 2-8 •...
Page 22: Functional Information
ETB registers or trace RAM, the AHB interface can be left unconnected. If this is done, all accesses to the ETB must be performed using the JTAG interface. A block diagram of the ETB11 module is shown in Figure 2-1 on page 2-3. 2.1.2 Global configurability The size of the trace RAM is configurable.
Page 23: Figure 2-1 Etb11 Module Block Diagram
Read/write control signals Addr[(RAW-1):0] AHB interface signals AHB interface Configuration Status TAP controller DBGTCKEN DBGTCK nDBGTRST DBGTMS DBGTDI DBGTDO nDBGTDOEN RBW=ETB_DATA_WIDTH RAW=ETB_ADDR_WIDTH Figure 2-1 ETB11 module block diagram ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 24: Operation
Trace capture is enabled using the control register. Trace data is continuously written into the trace RAM while the ETB11 is enabled and the trigger counter value is nonzero. Once the ETM11RV indicates a trigger by asserting TRIGGER, the trigger counter decrements once per word of trace stored.
Page 25 • AcqComp • Triggered • Full. These can be read at any time while trace capture is in progress. The status signals are cleared when TraceCaptEn is cleared. ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 26: Control Logic
Timing diagrams showing the operation of the control logic are given in Figure 2-2 and Figure 2-3 on page 2-7. Figure 2-2 Trace capture operation Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 27: Figure 2-3 Trace Read Operation
Functional Description TraceCaptEn RAMAddr UR+1 ReadData UD+1 RAMAccess ReadAddInc RegAccess ControlState Read Read Write Figure 2-3 Trace read operation ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 28: Data Formatter
TRACEVALID is asserted by the ETM11RV. You must set the port size to 32 bits and port mode to dynamic in the ETM11RV otherwise Unpredictable behavior might occur while using the ETB11. See the ETM Specification for details. Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 29: Trigger Delay Counter
(TraceCaptEn=0). The state of the triggered flag can be read from the Status Register. The Triggered flag is cleared when trace capture is disabled. AcqComp is output as a signal from the macrocell for possible use by ASIC logic. ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 30: Address Generation
Reading the RAM Read Pointer Register returns its current value, the RAM read address. The RAM Read Pointer Register is not affected by AHB reads from the RAM. 2-10 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 31: Bist Interface
ATPG vectors are created using Synopsys TetraMax. These enable the shadow logic around the ETB11 RAM to be tested provided that the TetraMax has access to a model of the RAM used. Greater than 99% stuck-at fault coverage can be achieved.
Page 32: Tap Controller
Functional Description TAP controller All registers in the ETB11 are programmed through the TAP controller or the AHB interface. Registers are accessed through scan chain 0. The TAP controller is connected in series with other TAP controllers on the chip.
Page 33: Table 2-1 Supported Public Instructions
3-4 for the current ID value. b1111 instruction connects a one-bit shift register, the BYPASS register, between BYPASS BYPASS DBGTDI and DBGTDO. Note The first bit shifted out is a zero. ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. 2-13...
Page 34 HCLK. CLK and DBGTCK can be asynchronous or synchronous. ETM11RV does not have DBGTCK but uses CLK and DBGTCKEN to gate the flops in the JTAG block. 2-14 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 35: Trace Ram Interface
An active HIGH write enable signal RAM data input bus An active HIGH output enable signal RAM data output bus The timing requirements for the ETB11 are described in Chapter 4 Timing Requirements. 2.9.2 Read access A timing diagram showing a read access from the Trace RAM to the Trace RAM interface is shown in Figure 2-5 on page 2-16.
Page 36: Figure 2-5 Read Access From Trace Ram Timing Diagram
A timing diagram showing a write access to the Trace RAM from the Trace RAM interface is shown in Figure 2-6. Dout Figure 2-6 Write access to Trace RAM timing diagram 2-16 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 37: Clocks, And Resets
Write transfer on page 2-22. 2.10.2 Resets There are the following resets: • nRESET resets all of the ETB11 registers in the CLK domain. nRESET must be synchronized to CLK using the circuit shown in Figure 2-7. ETB11 nDBGTRST nRESET...
Page 38 Functional Description • HRESETn is the AHB interface reset signal and is used to reset all of the registers in the AHB interface. 2-18 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 39: Ahb Transfers
HADDRReg, the registered version of HADDR that remains valid until HReq goes LOW, is valid. The CS and CRegRead signals that control read access of the ETB11 RAM and the ETB11 registers go HIGH for one cycle after CReq goes HIGH.
Page 40: Figure 2-8 Synchronization Logic Between Hclk And Clk Domains
In synchronous designs where HCLK is derived from CLK, HCLKEN is used to control the generation of HCLK and CLK is connected to the HCLK input of the ETB11. 2-20 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 41: Figure 2-9 Software Read Cycle With Asynchronous Clk And Hclk
Functional Description Figure 2-9 Software read cycle with asynchronous CLK and HCLK ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. 2-21...
Page 42: Figure 2-10 Software Read Cycle With Synchronous Clk And Hclk
A software read cycle with CLK and HCLK synchronous is shown in Figure 2-9 on page 2-21. The pipelined nature of the ETB11 data means that data takes more than a single cycle to perform a read (and write) operation. Wait states are inserted until the read cycle is completed.
Page 43 HWDATA), and the address is already valid on HADDRReg. The CS,WE, and RegWrite signals that control write access of the ETB11 RAM and the ETB11 registers then go HIGH for one cycle after CReq goes HIGH to perform the write access.
Page 44: Figure 2-11 Software Write Cycle With Asynchronous Clk And Hclk
Figure 2-11 Software write cycle with asynchronous CLK and HCLK Synchronous HCLK and CLK Software write cycles with CLK and HCLK synchronous (the SBYPASS signal is HIGH) is shown in Figure 2-12 on page 2-25. 2-24 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 45: Figure 2-12 Software Write Cycle With Synchronous Clk And Hclk
Functional Description Figure 2-12 Software write cycle with synchronous CLK and HCLK ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. 2-25...
Page 47 It contains the following sections: • About the programmer’s model on page 3-2 • Register descriptions on page 3-4 • Software access to the ETB11 using the AHB interface on page 3-11. ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 48: About The Programmer's Model
Programmer’s Model About the programmer’s model This section provides general information relevant to the ETB11 programmer’s model: • Register fields • Register map. 3.1.1 Register fields You must not access reserved or unused address locations because this can result in unpredictable behavior.
Page 49 Table 3-1 Register map (continued) Register number Type Description Decimal Binary b000 0111 Read/write Trigger Counter Register b000 1000 Read/write Control Register 9-127 b000 1001- Reserved b111 1111 ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 50: Register Descriptions
For the current implementation the ID value is 32’h2B900F0F . It is recommended that tools check the value of bits [27:1] to detect that the ETB11 is present. Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 51: Table 3-3 Ram Depth Register Bit Allocations
[31:0] Read-only RAM data depth This value is configurable in the RTL but must be fixed when the ETB11 is synthesized. 3.2.3 RAM Width Register, r2 This is a read-only register, that indicates the number of bits in each addressable entry in the RAM to the trace tools.
Page 52: Table 3-5 Status Register Bit Allocations
Programmer’s Model 3.2.4 Status Register, r3 The read-only Status Register contains ETB11 status flags. You can read it at any time. Register bit allocations for the Status Register are listed in Table 3-5. Table 3-5 Status Register bit allocations Name...
Page 53: Table 3-6 Ram Data Register Bit Allocations
You can use the read-only RAM Data Register, while trace capture is disabled, to return the contents of the ETB11 SRAM location addressed by the RAM Read Pointer Register. Reading this register increments the RAM Read Pointer Register and triggers a RAM access cycle.
Page 54: Table 3-8 Ram Write Pointer Register Bit Allocations
When read, the RAM Read Pointer Register returns the current trace RAM read address. You cannot write to this register if TraceCaptEn is HIGH. This register is not accessible from the AHB interface because the RAM is memory-mapped. See Software access to the ETB11 using the AHB interface on page 3-11. 3.2.7...
Page 55: Table 3-9 Trigger Counter Register Bit Allocations
Trace before The counter is set to a small value. Trace about The counter is set to half the number of entries in the ETB11 RAM. The register bit allocations for the Trigger Counter Register are listed in Table 3-9.
Page 56: Table 3-10 Control Register Bit Allocations
0 = Trace capture is disabled Control register bit 0 drives the TraceCaptEn signal. When TraceCaptEn is set the ETB11 SRAM is in write mode. If you attempt to read the RAM Data Register read while TraceCaptEn is set, then the contents of the SRAM are altered, resulting in the corruption of any stored trace data.
Page 57: Software Access To The Etb11 Using The Ahb Interface
Aliased trace RAM RAM base address (for example, 0x13900000 The base addresses of the ETB11 registers and the RAM are defined by the AHB decoder. Software access to registers is only enabled when bit 2 of the control register (SoftwareCntl) is set to 1. This is the default and is set to 1 on reset.
Page 58 The AHB interface is enabled when the SoftwareCntl bit of the control register and the SWEN signal are ANDed. The ETB11 registers and RAM accesses are controlled by separate read/write ports and each has their own separate HSEL input. This enables the ETB11 RAM to share the address space with main memory. 3.3.1...
Page 59 Chapter 4 Timing Requirements The timing requirements for the ETB11 interfaces are defined in this chapter. It contains the following sections: • AHB interface on page 4-2 • CLK domain on page 4-4 • IEEE1149.1 interface on page 4-6. ARM DDI 0275D...
Page 60: Chapter 4 Timing Requirements
>0% ohhdata Rising HCLK to AHB control outputs valid ovhcon AHB control outputs hold time from HCLK rising >0% ohhcon AHB data inputs setup to rising HCLK ishdata Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 61 AHB control inputs setup to rising HCLK ishcon AHB control inputs hold from rising HCLK ihhcon HRESETn input setup to rising HCLK ishresetn HRESETn input hold from rising HCLK ihhresetn ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 62: Clk Domain
Rising CLK to CLK domain outputs valid ovctrans CLK domain outputs hold time from CLK rising >0% ohctrans Rising CLK to MBISTDOUT output valid ovmbdtrans MBISTDOUT output hold time from CLK >0% ohmbdtrans rising Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 63 ETM interface inputs setup to rising CLK isetmtrans ETM interface inputs hold from rising CLK ihetmtrans nRESET input setup to rising CLK isnreset nRESET input hold from rising CLK ihnreset ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 64: Ieee1149.1 Interface
JTAG inputs setup to rising DBGTCK isttrans JTAG inputs hold from rising DBGTCK ihttrans nDBGTRST input setup to rising DBGTCK isntrst nDBGTRST input hold from rising DBGTCK ihntrst Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 65: Appendix A Signal Descriptions
Appendix A Signal Descriptions This appendix describes the ETB11 input and output signals. It contains the following sections: • Signal properties and requirements on page A-2 • Signal descriptions on page A-3. ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 66: Signal Properties And Requirements
Signal Descriptions Signal properties and requirements To ensure ease of integration of the ETB11 into embedded applications, and to simplify synthesis flow, the following design techniques have been used: • a single rising edge clock times all activity • all signals and buses are unidirectional •...
Page 67: Signal Descriptions
Signal Descriptions Signal descriptions Table A-1 lists the ETB11 input and output signals. Table A-1 Signal descriptions Clock Signal Name Type Description domain Output When HIGH indicates that trace ACQCOMP acquisition is complete. Input This clock times all operations in the Trace Buffer.
Page 68 Memory-mapped peripheral AHB transfer response. Provides additional information on the transfer status: 00 = OKAY 01 = ERROR 10 = RETRY 11 = SPLIT. ETB11 does not support splits and retries. ETB11 outputs an OK or ERROR response only/ HSELMEM HCLK Input Indicates that the ETB11 RAM has been selected for an AHB transfer.
Page 69 Input Indicates that the current trace information on TRACEOUTPUT is valid. TRIGGER Input Indicates that an ETM11RV trigger has occurred. a. Can be left unconnected during normal operation. ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved.
Page 71 Appendix B Integrating the ETB11 This section describes how to integrate the ETB11 if you are not using the ETK11 Integration Kit. It contains the following sections: • ASIC connections on page B-2 • Connecting to ETM11RV on page B-3 •...
Page 72: Asic Connections
Signal Connection information SWEN If the AHB interface is to be used to access the ETB11 registers and the ETB11 RAM, then this must be tied HIGH. Otherwise it must be tied LOW. ACQCOMP This is a status signal from the ETB11 that can be used to control on-chip logic. For example, ACQCOMP can be used to generate an interrupt request to the ARM processor in the system to indicate that the ETB11 is finished collecting trace information.
Page 73: Connecting To Etm11Rv
Integrating the ETB11 Connecting to ETM11RV Use the connection scheme listed in Table B-2 to connect the ETB11 to a generic trace port interface device, such as an ETM11RV. Table B-2 ETB11 to generic trace port interface connections ETB11 signal...
Page 74: Connecting The Etb11 In A 64-Bit Ahb System
If the code shown in Example B-1 is used then load/store multiple instructions that access the ETB11 have unpredictable results because these use both halves of the 64-bit bus at the same time. These accesses do not cause an AHB ERROR response, which normally cause a Data Abort, so the error is not seen by the system.
Page 75: Glossary
Advanced Microcontroller Bus Architecture (AMBA) AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
Page 76 JTAG boundary-scan architecture. The mandatory terminals are DBGTDI, DBGTDO, DBGTMS, and DBGTCK. The optional terminal is nDBGTRST. See Trace Port Analyzer. Glossary-2 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...
Page 77 For writes, writing to this location causes unpredictable behavior, or an unpredictable change in device configuration. Unpredictable instructions must not halt or hang the processor, or any part of the system. A 32-bit data item. Words are normally word-aligned in ARM systems. Word ARM DDI 0275D Copyright ©...
Page 79 B-3 BIST see MBISTADDR Data formatter 2-8 Boundary scan 1-4 Debug implementation 1-2 Design techniques ETB11 A-2 Identification Register 3-4 IEEE1149.1 interface signals 4-6 Instruction Register 2-13 ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. Index-1...
Page 80 SWEN A-5 RAM Width 3-5 TRACEOUTPUT A-5, B-3 RAM Write Pointer 3-8 TRACEVALID A-5, B-3 Status 3-6 TRIGGER A-5, B-3 Resets 2-17 Software access to ETB11 3-11 Index-2 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D...

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