Figure 8.7 Basic System Bus Interface - Analog Devices ADSP-2106x SHARC User Manual

ADSP-2106x
#2
BR BR 2 2 ADDR 31-0 ADDR
31-0
5
BR BR 1 1 BR BR 3-6
,
3-6 DATA DATA 47-0
47-0
3
ID ID 2-0
010
2-0
CS2 CS2
HBR HBR
HBG HBG
REDY REDY
WR WR
ACK
MS
MS 3-0
HBG HBG
REDY
REDY
HBR HBR
ADSP-2106x
#1
ADD ADDR R 31-0
BR BR 1 1
31-0
5
DATA 47-0 DATA
BR BR 2-6
47-0
2-6
3
ID ID 2-0
001
2-0
CS1 CS1
HBR HBR
HBG HBG
REDY
REDY
WR WR
ACK
MS
MS 3-0

Figure 8.7 Basic System Bus Interface

read or write signals. To avoid glitching the
are changing, the address comparator may be qualified by an address
latch enable signal from the system or by the system read or write
signals. These methods cause
read or write is deasserted or the address is changed. Because these
techniques deassert
occurs as part of each access. One can avoid this type of overhead by
HBG
latching during long sequences of bus accesses.
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Host Interface
RD
RD
3-0
WE WE
RD RD
OE OE
ACK
EXTERNAL
CS CS
3-0
MEMORY
ADDR ADDR
DATA
DATA
HBR
to be deasserted each time system
HBR
with each access, the overhead of an HTC
System Bus Interface
OE OE T/ T/R R
HBG HBG
HBR HBR
CS2
CS2 Address
CS1 CS1 Comparator
HBR
line when addresses
8
System Data Bus
Write
Read
REDY
System Address Bus
"Address Valid"
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