Link Common Control Register (Lcom) - Analog Devices ADSP-2106x SHARC User Manual

9.2.2

Link Common Control Register (LCOM)

The LCOM register contains status bits, packing status bits, and 2X clock
rate bits for each buffer. These bits are listed in Table 9.3.
Bit(s) Name Definition
0-1 L0STAT(0:1) Link buffer 0 status: 11=full, 00=empty,10=one word *
2-3 L1STAT(0:1) Link buffer 1 status: 11=full, 00=empty,10=one word *
4-5 L2STAT(0:1) Link buffer 2 status: 11=full, 00=empty,10=one word *
6-7 L3STAT(0:1) Link buffer 3 status: 11=full, 00=empty,10=one word *
8-9 L4STAT(0:1) Link buffer 4 status: 11=full, 00=empty,10=one word *
10-11 L5STAT(0:1) Link buffer 5 status: 11=full, 00=empty,10=one word *
12 LCLKX20 Transfer data at 2X the clock rate on Link Buffer 0
13 LCLKX21 Transfer data at 2X the clock rate on Link Buffer 1
14 LCLKX22 Transfer data at 2X the clock rate on Link Buffer 2
15 LCLKX23 Transfer data at 2X the clock rate on Link Buffer 3
16 LCLKX24 Transfer data at 2X the clock rate on Link Buffer 4
17 LCLKX25 Transfer data at 2X the clock rate on Link Buffer 5
18 L2DDMA** Enable 2-dimensional DMA
19 LPDRD** Disable internal pulldown resistor for LxCLK and LxACK
20 LMSP** Mesh multiprocessing enable (set to 0 for normal operation)
21-22 LPATHD** Mesh multiprocessing LPATH changeover delay:
00=no additional delay, 01=1 additional delay,
10=2 additional delays, 11=3 additional delays
23-25 reserved
26 LRERR0 Receive pack error status for Link Buffer 0:
1=incomplete, 0=complete
27 LRERR1 Receive pack error status for Link Buffer 1:
1=incomplete, 0=complete
28 LRERR2 Receive pack error status for Link Buffer 2:
1=incomplete, 0=complete
29 LRERR3 Receive pack error status for Link Buffer 3:
1=incomplete, 0=complete
30 LRERR4 Receive pack error status for Link Buffer 4:
1=incomplete, 0=complete
31 LRERR5 Receive pack error status for Link Buffer 5:
1=incomplete, 0=complete
Table 9.3 Link Common Control Register (LCOM)
Status bits are read-only.
* The code 01 does not appear as a valid status.
** Common to all link ports.
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