Handshake Mode - Analog Devices ADSP-2106x SHARC User Manual

6 DMA
0) in the SYSCON register.
Note that ACK (or REDY) is only deasserted during a write when the
EPBx FIFO buffer is full. ACK (or REDY) remains asserted at the end of
a completed block transfer if the EPBx buffer is not full. When reading,
the buffer will be empty at the end of the block transfer and ACK (or
REDY) will be deasserted if an additional read is attempted.
System-Level Considerations
Slave mode DMA is useful in systems with a host processor because it
allows the host to access any ADSP-2106x internal memory location
while limiting the address space the host must recognize—only the
address space of the ADSP-2106x's IOP registers. Slave mode DMA is
also useful for ADSP-2106x to ADSP-2106x DMA transfers.
Slave mode DMA has one drawback when interfacing to a slow host—
the fact that the external bus is held up during the transfer (whether
initiated by the ADSP-2106x or the host) and no other transactions can
proceed. To overcome this, the handshake DMA mode may be used. In
handshake mode, the host does not have to master the bus in order to
make a DMA request, nor does the ADSP-2106x (in master mode) have
to wait on the bus for the transfer to complete. Instead, the host asserts
DMARx
the pin. When the ADSP-2106x is ready to make the transfer,
it can complete it in one bus cycle. The following section provides
further details.

6.4.3.4 Handshake Mode

On the ADSP-21060 or ADSP-21062, DMA channels 7 and 8, for
external port buffers EPB1 and EPB2, each have a set of external
handshake controls.
signals for EPB1 and channel 7, and
request and grant signals for EPB2 and channel 8.
On the ADSP-21061, DMA channels 7 and 6, for external port buffers
EPB1 and EPB0, each have a set of external handshake controls.
DMAR1 DMAG1
and
channel 7, and
for EPB0 and channel 6.
These signals serve as a hardware handshake to facilitate DMA
transfers between the ADSP-2106x and an external peripheral device
that does not have bus mastership capability.
If external port DMA channel is enabled but the handshake
signals will not be used, the corresponding
6 – 42
should be kept high.
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DMAR1 DMAG1
and
DMAR2
are the request and grant signals for EPB1 and
DMAR2 DMAG2
and are the request and grant signals
are the request and grant
DMAG2
and are the
DMARx
signal