Analog Devices ADSP-2106x SHARC User Manual page 675

single-word data transfers
link port vs. link buffer
48-bit word
32-bit word
16-bit word
data memory
program memory
program memory data access
DMACx control registers
DMA control registers
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SHARC Glossary
(host processor) reads and writes to the EPBx external
port buffers, performed externally by the host or
internally by the ADSP-2106x core; these occur when
DMA is disabled in the DMACx control register
the link ports receive and transmit data on their
LxDAT data pins; the six independent link buffers
3-0
may be connected to any of the six link ports
usually implies instruction word, but may also imply
48-bit instructions and 40-bit extended-precision data
values that are transferred within 48-bit words; 48-bit
words use three 16-bit memory columns
standard 32-bit data word; uses two 16-bit memory
columns
16-bit short data word; uses one 16-bit memory column
region of memory in which 32-bit data words and
16-bit short words are stored; implies that the DM bus is
used for accesses (see the following sections in the
Memory chapter of this manual for details: "Overview,"
"Dual Data Accesses," and "On-Chip Memory Buses &
Address Generation")
region of memory in which 48-bit instruction words
and (optionally) 32-bit or 40-bit data words are stored;
implies that the PM bus is used for accesses (see the
following sections in the Memory chapter of this manual
for details: "Overview," "Dual Data Accesses,"
"Instruction Cache & PM Bus Data Accesses," and
"On-Chip Memory Buses & Address Generation")
when an ADSP-2106x instruction reads or writes data
over the PM Data Bus; the address is generated by
DAG2 on the PM Address Bus
the DMA control registers for the EPBx external port
buffers: DMAC6, DMAC7, DMAC8, and DMAC9
(corresponding respectively to EPB0, EPB1, EPB2,
and EPB3)
see "DMACx control registers"
G
G – 3