Analog Devices ADSP-2106x SHARC User Manual page 221

Handshake mode DMA is enabled when the HSHAKE bit is set to 1 in
the corresponding DMACx control register (DMAC7 or DMAC8 on an
ADSP-21060 or ADSP-21062; DMAC7 or DMAC6 on an ADSP-21061).
If the MASTER bit is 0, the ADSP-2106x handshakes by returning
DMAGx
. If the MASTER mode bit is 1, the DMA operates in paced
master mode.
DMA handshaking operates asynchronously at up to the full clock
speed of the ADSP-2106x. The data source/destination can be selected
to be either ADSP-2106x internal memory or external memory. It is
important to load the EC external count register whenever external
DMA transfers are being made.
MS
3-0
The memory select lines are deasserted during DMA transfers
between an external device and an ADSP-2106x because there is no
external memory space being accessed. The
asserted by the ADSP-2106x in external handshake mode because it is
providing the address and strobes for transfers between an external
DMA device and external memory.
Refer to Figure 6.8, DMA Handshake Timing with Asynchronous Requests.
The DMA handshake uses the rising and falling edges of
ADSP-2106x interprets a falling edge to mean "begin a DMA access"
and interprets the rising edge to mean "complete the DMA access."
To request an access of the EPBx buffer, the external device pulls
DMARx
low. The falling edge is detected by the ADSP-2106x and
synchronized to the processor's system clock. To be recognized in a
DMARx
particular cycle, the
specified in the data sheet; otherwise it may take effect in the following
cycle. When the ADSP-2106x recognizes the request, it begins to
arbitrate for the external bus, if it is not already the bus master or if the
buffer is not blocked (see discussion of blocked condition below). When
the ADSP-2106x becomes the bus master, it drives
DMAGx
ADSP-2106x will keep
deasserted. This allows the external device to hold the ADSP-2106x
until it is ready to proceed. Provided there are no pipelined requests,
DMAGx
will deassert in the cycle after
external device does not wish to extend the grant cycle, it can deassert
DMARx
immediately after asserting it, provided it meets the minimum
pulse width timing requirements specified in the data sheet. In this
DMAGx
case, will be a short pulse and the external bus will only be
used for one cycle.
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MS
3-0
lines are, however,
low transition must meet the setup time
DMAGx
DMARx
asserted until it sees
DMARx
is deasserted. If the
DMA 6
DMARx
. The
low. The
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