Host Interface Deadlock Resolution With Sbts - Analog Devices ADSP-2106x SHARC User Manual

When performing synchronous transfers, the host should use the same
number of wait states as are configured for multiprocessor memory space
wait states; otherwise the system may hang. This is configured by the
MMSWS bit of the WAIT register.
When an ADSP-2106x is responding to a synchronous read access, it
will only drive valid data for one cycle, even if the access is prolonged
by the host. Specifically, after the host synchronously asserts
ADSP-2106x will drive valid data only in the first cycle it asserts ACK
and will tristate the data bus during the following cycles, even if the
RD
host continues to assert
8.2.4 Host Interface Deadlock Resolution With
SBTS HBR
If and are both asserted, the ADSP-2106x will enter slave
HBG
mode. ACK, , REDY, and the data bus may all be active in slave
mode. If the ADSP-2106x was performing an external access (which
did not complete) in the same cycle that
the access will be suspended until
again.
This functionality, i.e. using
host /ADSP-2106x deadlock resolution. If
while an external DMA access is occurring,
until the access is completed. If
lock is set, the ADSP-2106x will tristate its bus signals but will not go
into slave mode.
See "Deadlock Resolution" in the "System Bus Interfacing" section of
this chapter for further details.
8.3 SLAVE DIRECT READS & WRITES
The host can directly access the internal memory and IOP registers of
an ADSP-2106x by simply reading or writing to the appropriate
address in multiprocessor memory space—this is called a direct read or
direct write. Each ADSP-2106x bus slave monitors addresses driven on
the external bus and responds to any that fall within its region of
multiprocessor memory space.
These accesses are invisible to the slave ADSP-2106x's core processor
because they are performed through the external port and via the
on-chip I/O bus—not the DM bus or PM bus. (See Figure 8.1.)
This is an important distinction, because it allows the core processor to
continue program execution uninterrupted.
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Host Interface
.
SBTS
SBTS
SBTS HBR
and
SBTS HBR
and are both deasserted
SBTS HBR
and together, can be used for
SBTS HBR
and
HBG
will not be asserted
SBTS HBR
and are asserted while bus
8
RD
, the
were asserted,
are asserted
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